fpga-field programmable gate arrays-research papers-2012 section 3
FPGA Based Wireless Multi-Node Transceiver and Monitoring System
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Ö Akin, I Basaran, R Sokullu, I Alan ,David Publishing , 2012 ,edutus.hu
Abstract: In recent years the variety and complexity of Wireless Sensor Network (WSN)
applications, the nodes and the functions they are expected to perform have increased
immensely. This poses the question of reducing the time from initial design of WSN
Design and FPGA Implementation of an Improved RNS Converter
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ABSTRACT The recently introduced four-moduli set {2n–1, 2n, 2n+ 1, 22n+ 1–1} have the
capability to provide high-performance residue number systems (RNS) due to its large
dynamic range and well-formed moduli. There have been two RNS-to-binary converters
FPGA Design for DDR3 Memory
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L Fischer ,2012
Page 1. FPGA Design for DDR3 Memory Sponsored by Teradyne, North Reading, MA The final
design is implemented on a Virtex 6 FPGA chip. The arbiter can achieve a maximum performance
of around 50 Gb/s, with the two systems reaching transfer rates of 25 Gb/s. Page 4. 3
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Metodología de diseño sobre FPGA en un curso de sistemas digitales
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JLU Aponte, AMG Correal, AF Guzmán ,ARTÍCULOS DE , 2012 ,ustabuca.edu.co
Resumen—Se presenta en este trabajo una metodología para el diseño de sistemas
digitales sobre FPGA (Field Programmable Gate Array). Esta metodología inicia con el
análisis de requerimientos del cliente y abarca hasta la implementación final en un
FPGA ImplementationDesign of Micro UART With Different Baud Rates
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M Kaur, R Mittal ,Journal of Information Systems and Communication. , 2012
Abstract-In this paper we are designing Micro UART has capable of performing 8-bit
Asynchronous data communication at different baud rates with the capability of error
detection such as Parity error, Overrun error, Framing Error. The maximum clock
Design and Implementation of I2c master controller on FPGA using VHDL
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JK Singh, M Tiwari, V Sharma ,International Journal of , 2012
Abstract-The focus of this paper is on I2C protocol following master controller. This controller
is connected to a microprocessor or computer and reads 8 bit instructions following I2C
protocol. The instructions are then processed and converted to instructions which follow
Implementation of Adaptive OFDM System Using FPGA
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MA Mohamed, AS Samarah, MIF Allah ,2012
Abstract OFDM is a modulation as well as multiplexing technique which is now widely used
in various high speed mobile and wireless communication systems because of its capacity
of ensuring high level robustness against interference. In this paper the design and
Design and Implementation of Reconfigurable Embedded Processor (REP) for AUV usingFPGA
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Abstract The superscalar pipeline is something that the REP architecture resembles. The
features that are similar in both architectures include rename, decode, fetch as well as in-
order front-end’s parts as substituted by dispatch units. The physical register file, execute
FPGA Design and Implementation of Multi-Filtering Techniques Using Flag-Bit and Flicker Clock
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Abstract Real time system is a condition where the processor is required to perform its tasks
within a certain time constraints of some processes or simultaneously with the system it is
assisting. Typically, it suffers from two main problems; delay in data processing and
FPGA Fuzzy Controller Design for Magnetic Ball Levitation
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HA Elreesh, B Hamed ,International Journal of Intelligent Systems, 2012
Abstract—this paper presents a fuzzy controller design for nonlinear system using FPGA. A
magnetic levitation system is considered as a case study and the fuzzy controller is
designed to keep a magnetic object suspended in the air counteracting the weight of the
Fuzzy Controller Design using FPGA for Sun Tracking in Solar Array System
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BM Hamed, MS El-Moghany ,International Journal of Intelligent , 2012
Abstract—The output power produced by high-concentration solar thermal and photovoltaic
systems is directly related to the amount of solar energy acquired by the System, and it is
therefore necessary to track the sun’s position with a high degree of accuracy. This paper
Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm
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ABSTRACT This paper compares FPGA-based full pipelined multiplierless FIR filter design
options. Comparison of Distributed Arithmetic (DA), Common Sub-Expression (CSE) sharing
and n-dimensional Reduced Adder Graph (RAG-n) multiplierless filter design methods in
Genetic Algorithm-based Neural Network For Accidents Diagnosis of Research Reactors OnFPGA
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AA Ahmed, NA Alfishawy ,Journal of American , 2012
Abstract: In a nuclear research reactors plant, a fault can occur in a few milliseconds, so
locating the fault might be of utmost importance due to safety, and other reasons.
Accordingly, there is an increasing demand for automated systems to diagnose such
FPGA based generalized architecture for Modulation and Demodulation Techniques
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SK Samaddar, A Sanyal, S Sanyal ,2012 ,jctjournals.com
Abstract-Here we design a modulator-demodulator circuit which can execute different
modulation schemes like-AM, ASK, BPSK, FSKQPSK. Both the LUT based
implementation and complete VHDL based implementation have done by using digital
Remote FPGA Lab for Enhancing Learning of Digital Systems
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F MORGAN, S CAWLEY, D NEWELL ,ACM Transactions on , 2012 ,remotefpga.com
Learning in digital systems can be enhanced through applying a learn-by-doing approach
on practical hardware systems and by using web-based technology to visualise and animate
hardware behaviour. The authors have reported the web-based Remote FPGA Lab (RFL)
FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS-II Based SOC
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BL Naresh, NVN Rao, AP Ramesh ,International Journal, 2012
ABSTRACT This paper presents a frame work for hardware acceleration for post video
processing system implemented on FPGA. The deblocking filter algorithms ported on SOC
having Altera NIOS-II soft core processor. SOC designed with the help of SOPC builder.
FPGA Realization of Braun’s Multipliers
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MH Rais, MH Al Mijalli, M Nisar ,Proceedings of the International , 2012
Abstract—In this study we investigate the design and implementation of Braun’s multipliers
using Very High speed integrated circuit Hardware Description Language and implemented
on Virtex-5 FPGA devices. The Virtex-5 FPGA devices including XC5VLX30, XC5VLX30T,
A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm
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X Guo, H Wang, V Devabhaktuni ,ISRN Bioinformatics, 2012 ,downloads.isrn.com
A design of systolic array-based Field Programmable Gate Array (FPGA) parallel
architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST
is a heuristic biological sequence alignment algorithm which has been used by
Implementation of Transient Signal Detection Algorithms on FPGA
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H GholamHosseini, K Li ,International Journal of Computer , 2012
ABSTRACT Radio transient signals are non-periodic and discrete obtained from high
energy physical processes in space. Most challenging issues in transient signal detection
are the speed and accuracy with which a signal can be detected. Cumulative Sum (
Implementation of Neural Network Back Propagation Training Algorithm on FPGA
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SL Pinjare, A Kumar ,International Journal of Computer , 2012
ABSTRACT This work presents the implementation of trainable Artificial Neural Network
(ANN) chip, which can be trained to implement certain functions. Usually training of neural
networks is done off-line using software tools in the computer system. The neural networks
FPGA and dSPACE based Sliding Mode Control of Boost Converter for PEM Fuel Cell Application
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B Kumari, RS Rana, CY Patil ,International Journal of , 2012
ABSTRACT This paper presents a non-linear dynamic model of a PEM (Proton Exchange
Membrane) fuel cell and its simulation in MATLAB. A single cell and three cells stack is
fabricated and simulation results obtained are validated experimentally with the dynamic
Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA
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Abstract—This brief compares the use of multiplierless and DSP slice-based cross-
correlation for IEEE 802.16 d orthogonal frequency division multiplexing (OFDM) timing
synchronization on Xilinx Virtex-6 and Spartan-6 field programmable gate arrays (FPGAs).
An FPGA Based Hardware Architecture for Network Flow Analysis
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P Rajeswari, N Nagarajan ,European , 2012 ,europeanjournalofscientificresearch.
Abstract Network monitoring and measurement have become more and more important in a
modern complicated network. With the rapid growth in communication, the network link
speed is increasing fastly. So the need for high speed monitoring of network flow has
Comparison Framework of FPGA-based GNSS Signals Acquisition Architectures
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J Leclère, C Botteron, PA Farine ,IEEE Transactions on , 2012 ,infoscience.epfl.ch
Systems signals using Code Division Multiple Access can be performed through classical
correlation or using a Fourier transform. These methods are well known but what is missing
is a comparison of their performance for a given hardware area or target. This paper
Accurate dynamic power model for FPGA based implementations
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C Najoua, B Mohamed, BM Hedi ,2012
Abstract This paper presents an accurate field programmable gate array (FPGA) of analytical
dynamic power models for basic operators at the RTL (Register Transfer Level) level. The
models are based on the frequency, the activity rate and the input precision by using the
FPGA Implementation of Single Bit Error Correction using CRC
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SP Pramod, A Rajagopal ,International Journal of , 2012
ABSTRACT Transferring data between two points is very essential, also the accuracy of the
transferred data is vital for some critical applications, but an error during the transmission of
data is very common. The Cyclic Redundancy Check (CRC) method is generally used for
HW\ SW IMPLEMENTATION OF IRIS RECOGNITION ALGORITHM IN THE FPGA
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H Raida, MA YassineAoudni ,International Journal of Engineering , 2012
Abstract: Recent years have seen the growth of new pattern recognition applications which
based on personal biometric characteristics. These applications are used for security, logical
or physical access control, etc. Iris recognition has been successfully deployed in several
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