fpga-field programmable gate arrays-research papers-2012 section 5





 Model-Based FPGA Embedded-Processor Systems Design Methodologies: Modeling, Syntheses, Implementation and Validation
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VA Akpan ,African Journal of ComputingICT January, 2012 ,ajocict.net
ABSTRACT The evolution of field programmable gate arrays (FPGAs) as custom-computing
machines for digital signal processing (DSP), real-time embedded and reconfigurable
systems development, embedded processors, and as co-processors for application

 A PROCESSOR BASED IMPLEMENTATION OF LAPPED BIORTHOGONAL TRANSFORM FOR JPEG XR COMPRESSION ON FPGA
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MR REHMAN, G RAJA ,Nucleus, 2012 ,thenucleuspak.org.pk
This paper describes a new methodology for implementation of Lapped Biorthogonal
Transform (LBT) used in JPEG XR Image compression. Due to sequential nature of LBT, we
present a processor based design that executes the instructions of LBT at higher speed. 

 FPGA Implementation of New Adaptive DWT-IDWT Lifting Technique for OFDM
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DK Varugheese, NJR Muniraj ,European , 2012 ,europeanjournalofscientificresearch.
Abstract As we move in to the future there is a rising demand for high performance, high
capacity and high bit rate wireless communication systems to integrate wide variety of
communication services such as high-speed data, video and multimedia traffic. In an 

 FPGA implementation of parametrical orthogonal transform-based experimental DSP devices
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G Valters ,2012 ,ortus.rtu.lv
Fast orthogonal transforms maintain a significant position in a wide range of signal
processing algorithms. Over the past decade particularly rapid progress has taken place in
the area of wavelets (one of the subclasses of orthogonal functions). For some years now, 

 FPGA Implementation of Efficient Radix-4 Multiplier with 3a Computation using Testable Reversible Logic
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A Nandal, T Vigneswaran ,European , 2012 ,europeanjournalofscientificresearch.
Abstract This paper contributes to the efficient realization of reversible logic based radix-4
multiplier architecture, as compared to the existing testable reversible logic. Reversible
circuits are of high interest in low power CMOS design, optical computing, quantum 

 On-Chip FPGA Memory Sub-System Architecture for Data Dependent Application
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P Deepa, C Vasanthanayaki ,European , 2012 ,europeanjournalofscientificresearch.
Abstract This paper presents an approach to on-chip memory sub-system architecture for
image compression algorithms especially for data dependent applications. The proposed
memory sub-system reduces the access latency and power by identifying the frequently 

 Case Studies in Acceleration of Heston’s Stochastic Volatility Financial Engineering Model: GPU, Cloud and FPGA Implementations
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C Delivorias, P Richtárik, M Takác ,2012 ,hpcfinance.eu
Abstract Here we present a comparative insight of the performance of the Heston stochastic
volatility model on different acceleration platforms. This model was tested against a
MacBook’s CPU, a Techila grid server hosted on Microsoft’s Azure cloud, a GPU node 

 Implementation of FIR Filter and FFT Systems on a STRATIX-III FPGA Processor
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BUV Prashanth ,International Journal of Computer , 2012
ABSTRACT In this paper, the implementation of DSP modules like FIR Filter and FFT based
systems are designed and implemented. The design is based on high performance FPGA
Cyclone II and implementation is done after functional and timing simulation. The 

 FPGA Based Kalman Filter
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E Pizzini ,2012
Page 1. FPGA Based Kalman Filter A Major Qualifying Project Report  1 Abstract This project was
undertaken to support the WPI Precision Personal Locator (PPL) project by prototyping an FPGA
implementation of a Kalman Filter to perform inertial system signal processing. 

 FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL
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LP Sree, B Satheesh ,International Journal of , 2012
ABSTRACT A Priority Interrupt Controller is a hardware designed chip which acts as an
overall system manager to efficiently handle the multiple interrupts that tend to occur from
the varied number of peripheral devices. Hence, it relieves the system? s CPU from the 

 Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA
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A Al Azad ,International Journal of Computer Applications, 2012
ABSTRACT In this paper, Data Encryption Standard (DES) and Triple Data Encryption
Standard (TDES) algorithm and their efficient hardware implementation in cyclone II Field
Programmable Gate Array (FPGA) is analyzed with the help of Cipher Block Chaining ( 

 FPGA Implementation of Low Complexity VLSI Architecture for DS-CDMA Communication System
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ABSTRACT The principal goal of this research work is focused on designing and then
testing the performance of source and channel coding and decoding circuits implemented
on FPGA for Code Division Multiple Access (CDMA) Transceiver using extremely simple 

 FPGA Interconnection Networks with Capacitive Boosting in Strong and Weak Inversion
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F Eslami ,2012 ,recoeng.ece.uvic.ca
ABSTRACT Designers of Field-Programmable Gate Arrays (FPGAs) are always striving to
improve the speed of their designs. The propagation delay of FPGA interconnection
networks is a major challenge and continues to grow with newer technologies. FPGAs 

A High-Performance FPGA Platform for Adaptive Optics Real-Time Control
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H Zhanga, Z Ljusica, G Hoveya ,SPIE Astronomical , 2012 ,spiedigitallibrary.org
ABSTRACT Adaptive Optics Real-Time Control systems for next generation ground-based
telescopes demand significantly higher processing power, memory bandwidth and I/O
capacity on the hardware platform than those for existing control systems. We present a 

 Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking
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BM Hamed, MS El-Moghany ,INTERNATIONAL JOURNAL OF , 2012
Abstract—The cell has optimum operating point to be able to get maximum power. To obtain
Maximum Power from photovoltaic array, photovoltaic power system usually requires
Maximum Power Point Tracking (MPPT) controller. This paper provides a small power 

 Automation of FPGA Implementation of Unitary Transforms Based on Elementary Generalized Unitary Rotation
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G Valters, P Misans ,ortus.rtu.lv
Elementary Generalized Unitary rotation (EGU-rotation) and the basics of building of
parametrical unitary transforms using EGU-rotations. EGU-rotation matrix (EGURM) is
multifaceted and takes 64 different shapes and up to several hundred faces for different 

 Dynamic Wi-Fi Reconfigurable FPGA Based Platform for Intelligent Traffic Systems
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M Hulea, GD Mois, S Folea , Applications and Solutions, S. Folea (ed.). ,cdn.intechweb.org
This chapter proposes a software and hardware platform based on a FPGA board to which a
Wi-Fi communication device has been added in order to make remote wireless
reconfiguration possible. This feature introduces a high level of flexibility allowing the 

 Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
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M Rani, H Vohra ,International Journal of Electronics ,ijecct.org
Abstract-FPGA implementation of 64-bit execute unit for VLIW processor, and improve power
representation have been done in this paper. VHDL is used to modelled this architecture.
VLIW stands for Very Long Instruction Word. This Processor Architecture is based on 

 Accelerating Short Read Mapping Using a Scalable FPGA Cluster
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C Olson, G Edvenson, B Kogon ,q8hw.com
Short read alignment software, such as BFAST (Blat-like Fast Accurate Search Tool)[1], is
one of the key tools in bioinformatics research. However, typical runtimes are measured in
hours or even days. Our implementation replaces a cluster of 260 quad-core Intel Xeon 

 Novel design of WiMAX multimode interleaver for efficient FPGA implementation using finite state machine based address generator
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BK Upadhyaya, SK Sanyal
Abstract—In this paper, we present a novel and efficient technique to model WiMAX
multimode interleaver using hardware description language. The hardware model is
implemented on FPGA platform. Our proposed interleaver consists of finite state machine 

 FPGA MODELLING AND REAL-TIME EMBEDDED CONTROL DESIGN VIA LABVIEW SOFTWARE: APPLICATION FOR SWINGING-UP A PENDULUM
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W Benrejeb, O Boubaker
Abstract-In this paper, Real-Time embedded control is designed via LabVIEW software for
swingingup a pendulum from its pending position to its upright position. Since the pendulum
system has a typical nonlinear instable model, the control problem is achieved using the 

 FPGA Implementation of Three-Phase Induction Motor Speed Control Using Fuzzy Logic and Logic Based PWM
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RP Dhobale, DM Chandwadkar
Abstract—This paper presents the design and implementation of FPGA based three phase
induction motor speed controller using fuzzy logic and logic based PWM technique. Logic
based pulse width modulation (PWM) generation method is used to vary the speed of 

 FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder
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J Tulasi, TV Lakshmi, M Kamaraju
Abstract-In this paper, we concern with designing and implementing a convolutional
encoder and Viterbi decoder which are the essential block in digital communication systems
using FPGA technology. Convolutional coding is a coding scheme used in communication 

 Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration
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Abstract In the paper, the activities which aim at developing a methodology of fault tolerant
systems design into FPGA platforms are presented. The methodology supports the detection
and localization of soft errors in the design and recovery mechanism which is based on 

 FPGA implementation of an embedded face detection system based on LEON3
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L Acasandrei, A Barriga ,elrond.informatik.tu-freiberg.de
Abstract-This paper presents an FPGA face detection embedded system. In order achieve
acceleration in the face detection process a hardware-software codesign technique is
proposed. The paper describes the face detection acceleration mechanism. It also 

 Arithmetic Unit Implementation Using A FPGA IEEE-754-2008 Decimal64 Floating-Point
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RG Surineedi, GSS Kumar, P Sunitha
Abstract: This paper describes the FPGA implementation of a Decimal Floating Point (DFP)
ALU (Arithmetic logic unit). The design performs addition, subtraction, multiplication and
division on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP 

 FPGA Implementation of Electrooculogram using Discrete Wavelet Transform
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V Priyanka, Y Padmasai, U Malini, P Chander ,irphouse.com
Abstract Neurological disorders affect about five percent of the population. Approximately
one percent of this group has been found to be epileptic. Epilepsy is a chronic neurological
disorder characterized by recurrent, unprovoked seizures. These seizures are due to 

 Optimized Median Filter Implementation on FPGA Including Soft Processor
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SS Tavse, PM Jadhav, MR Ingle ,ijetae.com
Abstract—The Median filter is an effective method for the removal of impulse-based noise
from the images. This paper suggests an optimized architecture for filter implementation on
FPGA. A 3×3 sliding window algorithm is used as the base for filter operation. Partial 

 Performance of Smart Antennas with FPGA Signal Processors over 3G Antennas
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B Bhuvaneswari, LB Karthikeyan
Abstract-Demands for increased capacity and better quality of service are driving the
development of new wireless technologies such as smart antenna arrays. The FPGAs
operate as powerful digital signal processing devices, which can meet the requirements of 



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