microprocessor research papers 12
Design methodologies for the PA 7100LC microprocessor
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M Bass, TW Blanchard, DD Josephson ,Hewlett Packard , 1995 ,mrynet.com
Engineers who wish to create a leading edge product with competitive performance,
features, cost, and time to market are often challenged to create design methodologies that
will enable them to succeed in their task. Decisions about the features of a product usually
DIVA: A Dynamic Approach to Microprocessor Verification Todd M. Austin taustin@ eecs. umich. edu Advanced Computer Architecture Laboratory University oF
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TM Austin ,Journal of Instruction-Level Parallelism, 2000 ,ece.umd.edu
Abstract Building a high-performance microprocessor presents many reliability challenges.
Designers must verify the correctness of large complex systems and construct
implementations that work reliably in varied (and occasionally adverse) operating
Automated correctness proofs of machine code programs for a commercial microprocessor
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R Boyer ,Automated Deduction—CADE-11, 1992 ,Springer
We have formally specified a substantial subset of the MC68020, a widely used
microprocessor built by Motorola, within the mathematical logic of the automated reasoning
system Nqthm, ie, the Boyer-Moore Theorem Prover [4]. Using this MC68020 specification,
Ramp: A model for reliability aware microprocessor design
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J Srinivasan, SV Adve, P Bose, J Rivers ,IBM Research Report, 2003 ,cs.utexas.edu
Abstract This report introduces RAMP, an architectural model for long-term processor
reliability measurement. With aggresive transistor scaling and increasing processor power
and temperature, reliability due to wear-out mechanisms is expected to become a
The Alpha 21264 microprocessor: Out-of-order execution at 600 MHz
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RE Kessler ,Hot Chips, 1998
Some Highlights z Continued Alpha performance leadership y 600 Mhz operation in 0.35 u
CMOS6, 6 metal layers, 2.2 V y 15 Million transistors, 3.1 cm2, 587 pin PGA y Specint95 of
30+ and Specfp95 of 50+ y Out-of-order and speculative execution y 4-way integer issue y
A framework for microprocessor correctness statements
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M Aagaard, B Cook, N Day ,Correct Hardware Design and , 2001 ,Springer
Most verifications of out-of-order microprocessors compare state-machine-based
implementations and specifications, where the specification is based on the instruction-set
architecture. The different efforts use a variety of correctness statements, implementations,
DDD-FM9001: Derivation of a verified microprocessor
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B Bose ,Correct hardware design and verification methods, 1993 ,Springer
The DDD-FM9001 is a 32-bit general purpose microprocessor formally derived directly from
Hunt’s mechanically verified Nqthm FM9001 microprocessor specification. The exercise was
part of a project to construct an implementation of the FM9001 by applying the DDD
A Holter-type, microprocessor-based, rehabilitation instrument for acquisition and storage of plantar pressure data
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ZO Abu-Faraj, GF Harris ,Journal of , 1997 ,rehab.research.va.gov
Abstract—A Holter-type, microprocessor-based, portable, inshoe, plantar pressure data
acquisition system has been developed. The system allows continuous recording of
pressure data between the sole of the foot and the shoe during the performance of daily
A framework for superscalar microprocessor correctness statements
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MD Aagaard, B Cook, NA Day ,International Journal on , 2003 ,Springer
Abstract. Most verifications of superscalar, out-of-order microprocessors compare state-
machine-based implementations and specifications, where the specification is based on the
instruction-set architecture. The different efforts use a variety of correctness statements,
The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor
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BC Brock ,Formal Methods in System Design, 1997 ,Springer
We present the full formal semantics of the DUAL-EVAL hardware description language.
DUAL-EVAL is a hierarchical, occurrence-oriented simulator for synchronous Mealy
machines. We briefly describe the FM9001 microprocessor, whose design has been
Power-performance modeling and tradeoff analysis for a high end microprocessor
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We describe a new power-performance modeling toolkit, developed to aid in the evaluation
and definition of future power-efficient, PowerPCTM processors. The base performance
models in use in this project are:(a) a fast but cycle-accurate, parameterized research
Automated proofs of object code for a widely used microprocessor
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Y Yu ,1992 ,cs.utexas.edu
First, I w ant to than k my thesis advisor B ob B oyer. He has been an immense source of k
no w ledge, ideas, and ins p iration. W ithout his su pp ort (intellectual and financial), this w
or kw ould be im p ossible. I w ould lik e to than k my committee members W oody B
Transistor count and chip-space estimation of simplescalar-based microprocessor models
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M Steinhaus, R Kolla , of the Workshop , 2001 ,informatik.uni-augsburg.de
Abstract This paper proposes a chip space and transistor count estimation tool, which
receives its input from the baseline architecture and the configuration file of the
microarchitecture performance simulator sim-outorder of the SimpleScalar Tool Set. The
Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology
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WW Hu, JY Zhao, SQ Zhong, X Yang ,Journal of Computer , 2007 ,Springer
Abstract This paper introduces the microarchitecture and physical implementation of the
Godson-2E processor, which is a four-issue superscalar RISC processor that supports the
64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and
Chip- Package Resonance in Core Power Supply Structures for a High PowerMicroprocessor
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LD Smith, RE Anderson ,target, 2001 ,si-list.net
Abstract Advanced microprocessors have high current demands at low voltage and require
low impedance power across a broad frequency range. Silicon circuits want to look out from
their power terminals and see a power supply impedance that is less than or equal to a
How microprocessor relays respond to harmonics, saturation, and other wave distortions
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SE Zocholl ,Proceedings of the 24th , 1997 ,sistemaselectricos.com
Abstract The magnetics and mechanisms of electromechanical relays are difficult to
formulate, and their characteristics are obtained mainly from experimental test data, As a
result, exactly how relays respond, or should respond, to harmonics, saturation, and wave
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor
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R McInerney, K Leeper, T Hill, H Chan ,Proceedings of the , 2000 ,cs.york.ac.uk
Itanium™ Microprocessor It will develop a repeater solution for a net that is electrically sound
and will then deal with the problem of implementing thousands of such solutions in the
microprocessor’s floorplan, RTL, schematic, layout and timing databases.
Relating multi-step and single-step microprocessor correctness statements
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M Aagaard, N Day ,Formal Methods in Computer-Aided Design, 2002 ,Springer
A diverse collection of correctness statements have been proposed and used in
microprocessor verification efforts. Correctness statements have evolved from criteria that
match a single step of the implementation against the specification to seemingly looser,
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