microprocessor research papers 11

microprocessor

microprocessor-71-2014

A practical zero-knowledge protocol fitted to security microprocessor minimizing both transmission and memory
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Zero-knowledge interactive proofs are very promising for the problems related to the verification of identity. After their (mainly theoretical) introduction by S. Goldwasser, S. Micali and C. Rackoff (1985), A. Fiat and A. Shamir (1986) proposed a first practical solution: the

Automatic verification of pipelined microprocessor control
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We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automatically compares a pipelined implementation to an

The design of an asynchronous microprocessor
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Prejudices are as tenacious in science and engineering as in any other human activity. One of the most ?rmly held prejudices in digital VLSI design is that asynchronous circuits-aka self-timed or delay-insen-sitive circuits--are necessarily slow and wasteful in area and

Dynamic voltage scaling on a low-power microprocessor
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ABSTRACT P ow er consumption is the limiting factor for the functionality of future wearable devices. Since in teractiv e applications like wireless information access generate bursts of activities, it is important to match the performance of the wearable device accordingly. This

MIPS R4000 microprocessor user s manual
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Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and/or in similar or successor clauses

A proof of correctness of the VIPER microprocessor: The first level
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The Viper microprocessor designed at the Royal Signals and Radar Establishment (RSRE) is one. of the first commercially produced computers to have been developed using modern formal methods. Viper is specified in a sequence of decreasinglyAbstract levels. In this

Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISCmicroprocessor
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performance). This new implementation of the Alpha architecture achieves SPECint92/SPECfp92 performance of 345/505 (estimated). At these performance levels,

Verifying Safety Properties of a PowerPC- Microprocessor Using Symbolic Model Checking without BDDs
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In Bounded Model Checking with the aid of satisfiability solving (SAT) was introduced as an alternative to symbolic model checking with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded

Power reduction techniques for microprocessor systems
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Power consumption is a major factor that limits the performance of computers. We survey the state of the art in techniques that reduce the total power consumed by a microprocessor system over time. These techniques are applied at various levels ranging from circuits to

Microprocessor design verification
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The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general-purpose, von Neumann processor whose design-level (gate-level) specification has been verified with

Dynamic voltage scaling and the design of a low-power microprocessor system
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ABSTRACT This paper describes the design of a low-power microprocessor system that can run between 8Mhz at 1.1 V and 100MHz at 3.3 V. The ramifications of Dynamic Voltage Scaling, which allows the processor to dynamically alter its operating voltage at run-time, will be

A 160-mhz, 32-b, 0.5-w cmos risc microprocessor
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As personal digital assistants (PDA s) move into the next generation, there is an obvious need for additional processing power to enable new applications and improve existing ones. While enhanced functionality such as improved handwriting recognition, voice recognition

The design and implementation of an asynchronous microprocessor
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The author s first degree was in Electronics at the University of Manchester Institute of Science and Technology (UMIST). An MSc in System Design at the Computer Science Department of the University of Manchester was completed the following year. The author

Trace table based approach for pipelined microprocessor verification
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This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data- dependent hazards. Our principal technique models the trace of executed instructions

Ultra low-cost defect protection for microprocessor pipelines
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ABSTRACT The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing

The First Aysnchronous Microprocessor: The Test Results
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We have designed the ?rst entirely asynchronous (also called self-timed or delayinsensitive) microprocessor. The design was reported at the Deccnnial Caltech Conference on VLSI, last March. The conference paper is included here as an appendix. Since the chips had not

Symbolic simulation of the JEM1 microprocessor
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Symbolic simulation is the simulation of the execution of a computer system on an incompletely defined, or symbolic, state. This process results in a set of expressions that define the final machine state symbolically in terms of the initial machine state. We

A history of microprocessor development at Intel
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Few advertisements have proved to be as prophetic as one that appeared in the November year-old manufacturer of MOS and bipolar RAMs with annual sales of $9 million and

Developing microprocessor based expert models for instrument interpretation
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ABSTRACT We describe a scheme for developing expert interpretive systems and transferring them to a microprocessor environment The scheme has been successfully implemented and tested by producing a program for interpreting results from a widely

The findit flashlight: Responsive tagging based on optically triggered microprocessor wakeup
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We have designed an active tagging system that responds to a coded optical beam from several meters away. The tags contain a minimalist microprocessor that ambiently operates in shutdown mode and, upon detecting particular frequency components in the AM-

A parallel genetic algorithm for multi-objective microprocessor design
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ABSTRACT The microprocessor chip designer must solve the problem of partitioning millions of transistors into an arbitrary number of hardware structures within a ?nite chip area toward achieving maximum performance. This combinative complexity is compounded by a

Evaluating the human engineering of microprocessor-controlled operating room devices
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ABSTRACT Although human engineering features are widely appreciated as a potential cause of operating room incidents, evaluating the human engineering features of devices is not widely understood. Standards, guidelines, laboratory and field testing, and engineering

Compiling for the CRISP Microprocessor
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ABSTRACT In this paper we present code generation considerations for the AT&T CRISP microprocessor. The architecture of CRISP is different from either current CISC or RISC machines in a number of ways. This opens the opportunity for several new types of

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