# Nanotechnology overview

Although today s electronic devices can be traced from the electric light bulb and the emissions that were called the Edison Effect in 1883, the focus will be on the more recent advances in electronics. From the 1950 s through today in 2004, significant strides have been made in improving the technology of designing computers and the technology implementing digital systems. In the 1950 s, the logic designer synthesized Boolean functions with AND, OR, NAND, and NOR logic gates. Minimization procedures such as the Quine-McCloskey algorithm reduce the number of liters in the function which reduced the number of input diodes, the major component in the AND, OR, NAND, and NOR logic gates. In the early 1960 s, the transistor replaced the diode as the major component in logic gates. Since the transistor lent itself directly to the realization of the NAND and NOR functions, the NAND and NOR logic models superseded the AND and OR logic gates. Many algorithms have been developed to synthesize functions with economical networks of NAND and NOR logic models [2, 3]. Hellerman [3, 4] has constructed catalogs of the NAND and NOR logic models for all three-variable functions. Semiconductor technology was extended to the development of integrated circuits that contained several transistors for the same cost as one transistor if the number of pins remained constant. Integrated circuits which contained 10 to 30 transistors were extended to ASICs and SOCs which contain millions of transistors. To take advantage of the additional complexity available with integrated circuits, ASICs, and SOCs, and a new synthesis procedure are needed. Also, the new synthesis procedure is needed to be based on a new type of model to create digital functions in ASICs and SOCs. Currently, designers extensively use Intellectual Property (IP) and libraries of circuits to implement ASICs and SOCs. IP and libraries are created by using a variety of rules with some circuits maximizing performance, some circuits minimizing power, other circuits minimizing the number of circuit blocks, some minimizing interconnect, and still others minimizing area. A resulting mixture of assorted rules, blocks of IP and libraries are stitched together as the design. The cost of purchasing or using IP and libraries is very expensive. In addition, the cost and the design which are far from optimum are reaching levels that are in excess of the financial returns possible for many designs. To determine the best logical building block, Patt [5, 6] analyzed and proposed a family of logic gates (the WOS gates) and studied extensively the three-variable case. The three-input WOS gate realizes the function 2D in our terminology. For three-variables, these gates perform significantly better then the traditional NAND and NOR gates. Patt catalogued realizations of all three-variable functions and has given an algorithm for the synthesis of functions of more than three-variables using multi-input WOS gates. To better understand the various characteristics of the single best Optimum Gate (O-Gate), a more detailed investigation of the 16 complete three-variable functions (including the 2D function) as given by Kudielka and Olivia [7] is required. The criterion used to judge if a single gate type more efficiently generates a function is based on (a) the number of gates used and (b) the amount of interconnect required in the realization of all three-variable functions. G. Opsahl [8] performed an analysis of the 16 functions to determine the best Optimum Gate, the O-Gate, and identified several important characteristics of the 2D function. The 2D function has the least amount of interconnect and is the only one of the 16 complete three-variable functions which is complete in two logic levels. Also, the 2D (the O-Gate) has three properties that are related to efficient generation of functions. Extending the O-Gate to four-variables led to the discovery of the four-variable logic gate realizing the function 2CD9. This function also has the property of realizing all four-variable functions in two logic levels and was demonstrated by an exhaustive investigation of all four-variable functions. The 2CD9 function, however, does not correspond to Patt s four-variable WOS gate. It was also demonstrated that the four-variable WOS gate is not logically complete in two levels. Also, G. Opsahl derived an algorithm containing the 2D and 2CD9 to extend the O-Gates beyond 4 variables. Since the cost of generating different types gates significantly increases the cost of designing ASICs and SOCs as well as integrated circuits, a single O-Gate that is used as the only gate in a design can significantly reduce the design time and manufacturing cost of the component. Since the engineer s design tools need only focus on the implementation with a single gate type, the cost to implement the engineer s tools by EDA vendors is less. Also, with these tools, engineers would be able to easily make design decisions since the decision criteria would be related to the interconnect and the number of gates. Since there would be only one gate repeatedly placed in the component, the gate could be easily replicated throughout the component and therefore the component would be less expensive to manufacture. There are currently gate arrays and FPGAs that might be considered a form of implementing these types of components. Although performance times are important, design time, manufacturing costs and power consumption are more important. Design time is shorter when there are fewer gates (the O-Gate has 71% fewer gates) and less interconnect (the O-Gate has 68% less interconnect). Since there are fewer gates and much less interconnect, there is substantially less time required by engineering design tools to place the gates and route the interconnect of the design. With the same sized O-Gate and NAND, manufacturing costs are reduced because more parts are produced from the same size die and reliability (yield or number of good devices per die ) increases due to the smaller sized part. The smaller parts are the result of the significant reduction in the number of gates in a part as well as less space required for the smaller amount to connections to stitch the gates together. Also, less interconnect space results in a reduction in the number of layers that need to be forced to stitch the interconnect of a design. The fabricated part needs significantly less power to operate due to fewer gates and due to less interconnect. If the power is the same for both gates, the fabricated part needs 71% less power due to fewer gates. However, perhaps particularly important for semiconductor technology, 68% less interconnect will reduce the power also. Since power related to the interconnect in semiconductors is: Power = C * V 2 / 2 where C is the capacitance to be charged (capacitance of the device, the capacitance of the interconnect, etc.) and V is the voltage (typically ranging from .8 volts to 5 volts with lower voltages preferred). If the capacitance and the voltage for both gates are the same, then there is 68% reduction in power due to the 68% reduction in interconnect. However, due to the amount and density of NAND interconnect, the capacitance for each NAND interconnect is probably higher and therefore the power is higher. Although semiconductor technology has begun to reach its limits, a variety of techniques have been used to extend semiconductor technology including the use of external fans to reduce the operating temperature caused by power dissipation and packaging to reduce interconnect to, from, and within the component. While a new technology is refined, perhaps semiconductor technology advancements can be continued with O-Gates and Reversible Logic.

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