vlsi research papers 2012-103
ENGINEERING RESEARCH PAPERS

vlsi research papers 2012-103




Bode Stability Analysis for Single Wall Carbon Nanotube Interconnects Used in 3D-VLSICircuits
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SH Nasiri, R Faez, B Davoodi, M Farrokhi ABSTRACT Bode stability analysis based on transmission line modeling (TLM) for single wall carbon nanotube (SWCNT) interconnects used in 3D-VLSI circuits is investigated for the first time. In this analysis, the dependence of the degree of relative stability for SWCNT

Vlsi Design of Cache Compression in Microprocessor Using Pattern Matching Technique
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ABSTRACT Microprocessors speeds have been increasing faster than speed of off-chip memory. When multi processors are used in the system design, more processors require more accesses to memory. Thus it raises a wall between processor and memory.

VLSI Design for Multi-Sensor Smart Systems on a Chip
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L Sellami, RW Newcomb Sensors are becoming of considerable importance in several areas, particularly in healthcare. Therefore, the development of inexpensive and miniaturized sensors that are highly selective and sensitive, and for which control and analysis is present all on one

Power Efficient VLSI Architecture for IIR Filter using Modified Booth Algorithm
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C TT II, C EE ABSTRACT Now a days various techniques have been developed for reducing the power consumption of VLSI designed nano-chips, such as pipelining and parallel processing, reducing the dynamic power, voltage scaling, clock gating etc. to increase the processing

Placement Migration Based On Diffusion Process For Future VLSI Design
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RPDKES Murthy, KS Rajan ABSTRACT The VLSI placement problem is to place the objects into fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose we use new type of placement method,placement migration

Design and Implementation of Memory-based Cross–Talk Reducing Algorithm to Eliminate Worst Case Crosstalk in On-Chip VLSI Interconnect
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S Singha, GK Mahanti ,International Journal of Soft Computing ABSTRACT Cross-talk induced Delay and power consumption are two of the most important constraints in an on-chip bus design. In same metal the ratio of cross-coupling capacitance between adjacent on-chip wires is quite larger. As a consequence, cross-talk interference

VLSI and Algorithms for High-Speed Arithmetic
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AA Liddicoat, MJ Flynn ,arith.stanford.edu ABSTRACT Area, latency, and process technology have a considerable impact on the cost- performance characteristics of floating point unit (FPU) design. Quantitative design metrics allow the FPU designer to make knowledgeable tradeoffs. Additionally, new algorithms

On the design of 2-port SRAM memory cells using PNPN diodes for VLSI application
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X Tong, QL HaoWu, H Zhong, H Zhu, D Chen, T Ye ,in4.iue.tuwien.ac.at ABSTRACT A novel 2-port vertical PNPN diode memory cell expected to increase the SRAM integration density was proposed in this work. Its optimization design to meet the power consumption and the operational speed requirements in conventional VLSI applications

Impulse Noise Removal using Spatial Threshold Value with Efficient VLSI Architecture
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N Kasthuri, CS Manikandababu ABSTRACT Data acquisition is the most important task for any system or application that includes signals. The principal source of impulse noise in digital image arises during image acquisition and transmission. The main objective of this paper is to reduce the impulse

VLSI Implementation of Densely Packed Decimal Converter to and from Binary Coded Decimal using Reversible Logic Gates
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SR Hussian, VN Nayak, F Noorbasha, S Dayasagar ABSTRACT The Binary Coded Decimal encoding has always dominated decimal arithmetic algorithms and their hardware implementation by virtue is ease of conversion between machine-and human-readable formats, as well as a more precise machine-format

VLSI Design of a 16-bit Pipelined RISC Processor
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T Chhabra, MT Khan ABSTRACT In this paper we have described the design of a 16-bit pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The

A TWO-STEP BINARY PARTICLE SWARM OPTIMIZATION APPROACH FOR ROUTING IN VLSI
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Abstract. Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm

Decreasing the Propagation Delay in DOMINO Structure in VLSI Circuits
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E Abiri, M Mirzazadeh, MR Salehi ABSTRACT In this article, a new technique is presented to reduce the propagation delay (tp) in DOMINO structure. This technique can be used in other structures such as NORA and PSEDO. The base of this technique is to discharge the Cgd in transistors in precharge

Reconfigurable VLSI architecture for FFT computation
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SS Kashyap ABSTRACT Parallel-prefix adders (also known as carry tree adders) are known to have the best Performance in VLSI designs. The Design of the three types of carry-tree adders namely Kogge-Stone, sparse Kogge-Stone, and spanning carry look ahead adder is done

Universal Rotate Invert Bus Encoding for Low Power VLSI
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M Shankaranarayana Bhat, DY Jahnavi ,International Journal ABSTRACT Power dissipation is an important design constraint in today s CMOS VLSI design and is addressed widely by the researchers across the globe. Switching activity is one of the factors that affect dynamic power in a chip and several publications have

Modeling and Prediction of Coupling Effects in Nanoscale VLSI Circuits
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YI Bontzios, MG Dimopoulos, AA Hatzopoulos ABSTRACT In this work, three approaches are presented for computing the resistive and capacitive coupling in VLSI circuits. The proposed methods are expressed in closed-form and are fast, accurate, scalable, and technology independent. They are validated against

AN ANALYTICAL APPROACH TO DESIGN VLSI IMPLEMENTATION OF LOW POWER, HIGH SPEED SRAM CELL USING SUB-MICRON TECHNOLOGY
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ABSTRACT The present title discloses a design and analysis of high speed Static Random Access Memory (SRAM) cell to develop low power consumption. The Low-Power and Highperformance CMOS devices are an industry needs these days. Among the various

Optimization of VLSI Architectures for DTW
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ABSTRACT In data mining and time series recognition applications Dynamic Time Warping (DTW) is a very popular method. It can produce accurate results provided its originality is preserved. But its lethargic nature has been inspiring development of its hardware based

M. Tech (VLSI) SCHEME OF EXAMINATION
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M ESE ,ycce.edu OBJECTIVES The students shall gain proficiency in subjects like the basic design of theory involved in VLSI for signal processing and communication systems, various software tools related to VLSI, Signal Processing and Communication Systems.

VLSI IMPLEMENTATION OF CORDIC ALGORITHM
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D Ghai, K Singh ,ampublisher.com ABSTRACT The CORDIC algorithm is used to calculate a wide variety of functions. It is hardware efficient algorithm. CORDIC is based on shift and adds operations. It consists of three addersubtractors, three shift registers and one look-up table. This paper presents

A VLSI Architecture for Output Probability and Likelihood Score Computations of HMM-Based Recognition Systems
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K Nakamura, R Shimazaki, M Yamamoto, K Takagi ,ebooks.narotama.ac.id Due to their effectiveness and efficiency for user-independent recognition, hidden Markov models (HMMs) are widely used in applications such as speech recognition (word recognition, connected word recognition and continuous speech recognition), lip-reading

EFFICIENT FAULT COVERAGE VLSI ARCHITECTURE FOR LFSR BASED IMAGE WATERMARKING SRAM
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S Jagadeesh, SB Kumar, M Ashok ABSTRACT Recent advances in the development of image watermarking algorithms had made a rapid change in the authenticated information resource sharing. Among all techniques of image watermarking and storing watermarked image bits in SRAM (Static Random Access

A New Technique to Decrease Leakage Power in VLSI Circuits
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K Sridhar, LN Rao, S Amshala, MS Uddin ABSTRACT Motivated by emerging battery-operated application on one hand and shrinking technology of deep sub micron (DSM) regime on the other hand, leakage power dissipation is rapidly playing a significant role in the total power dissipation as threshold voltage

PARTITIONING ALGORITHMS IN VLSI PHYSICAL DESIGNS–AReview
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ABSTRACT Initial electronic design automation is concerned with the design and production of VLSI systems. The next important step in creating a VLSI circuit is Physical Design. Physical design problems are combinatorial in nature and of large problem sizes. Due to its

Design of Adder in Multiple Logic Styles for Low Power VLSI
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KVS Reddy, C Venkataiah ABSTRACT The main consideration for design and implementation of various logics and Arithmetic functions, such as an adder, are the choice of basic pass transistor approach due to their high operating speed and low power dissipation. The main objective of this paper

Analog VLSI Implementation of Neural Network Architecture for Signal Processing
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N Chasta, S Chouhan, Y Kumar ,International Journal ABSTRACT With the advent of new technologies and advancement in medical science we are trying to process the information artificially as our biological system performs inside our body. Artificial intelligence through a biological word is realized based on mathematical

High Speed Continuous-Time Bandpass S? ADC for Mixed Signal VLSI Chips
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PA HarshaVardhini, M MadhaviLatha ,International Journal ABSTRACT With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (S?) converter is a popular technique

VL9221 CAD FOR VLSI CIRCUITS LTPC
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UIVD METHODOLOGIES , -2009 ME APPLIED ELECTRONICS II TO IV ,annauniv.edu 20 UNIT II DESIGN RULES 9 Layout Compaction-Design rules-problem formulation-algorithms for constraint graph compaction-placement and partitioning-Circuit representation-Placement algorithms-partitioning UNIT III FLOOR PLANNING 9 Floor planning concepts-shape

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