ENGINEERING RESEARCH PAPERS

adc analog to digital converter research papers 2015 IEEE PAPER




A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply
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Abstract:A SAR ADC incorporates two VCOs and a TDC as a multi-bit quantizer to improve the conversion speed. Using background calibration and realized in 45-nm technology, the ADC exhibits an SNDR of 68 dB and an FOM . step at Nyquist. The conversion

Reference Circuit Design for a SAR ADC in SoC
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A typical Analog-to-Digital Converter (ADC) compares an input voltage with a reference voltage and generates a digital code corresponding to the input voltage level. Equation 1 on page 1 gives the relation between ADC outputs and input and reference voltage for an

Radiation-Tolerant SAR ADC Architecture and Digital Calibration Techniques
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Our (TxACE, UTD) goals and approaches: 12/14 bit, 40/80 MS/s, 25 mW, 1.2 V, 65-nm CMOS SAR architecture [1] and digital calibration [2, 3] TID results presented at

Detection of Coloured Objects by the Implementation of Sigma Delta ADC
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Abstract:Colour Detection has became much important in modern applications. High- performance analog to digital converter collectively referred to as sigma delta converters has been implemented at the first stage which is highly significant in recent commercial

A 1-Mega Pixels HDR and UV Sensitive Image Sensor With In-terleaved 14-bit 64Ms/s SARADC
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terleaved 14-bit 64Ms/s SAR ADC Ruijun Zhang Master of Science Thesis sensor and SAR ADC This chapter gives an overview of the CMOS image sensor working principle, most commonly- used pixel structures, HDR methods and successive approximation ADC (SAR ADC).

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator
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Abstract:A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of

A 10-bit 10MS/s differential straightforward SAR ADC
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Abstract: A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is

A Low Power Non-Linear ADC for Neural Signal Recording in Brain Machine Interfaces
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Abstract To benefit from the advantages associated with digital signal processing and also digital data communication, it is usual in the design of biomedical signal recording devices to convert biomedical signal into digital. As a result analog to digital convertors (ADCs) are

Design and Implementation of Quantum Voltage Comparator for Flash ADC in 0.3 µm CMOS Technology using Static Electric 9.05 CAD Tool
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One of the major problems in the Threshold Inverter 1 Quantization (TIQ) flash ADC is a noise susceptibility of the TIQ comparator. Because the TIQ comparator, which consists of two cascaded inverters, has a singleended input, the comparator is very sensitive to

Noise-Shaping Cyclic ADC Architecture
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Design Techniques for 50GS/s ADC
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These applications typically require relatively modest resolution–~ 4-6 ENOB. Most state- ofart solutions with a high degree of interleaving achieve either relatively degraded energy efficiency [3],[4] or lower-than-Nyquist 3dB ERBW [6]. These tradeoffs arise due to several

A 43µwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180 nm CMOS Technology
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Abstract The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems
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Abstract:This paper presents a power and area efficient SAR ADC for multi-channel near threshold voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive array (S-DCA) structure with shifted input range for ultra low-

Analysis and Design of High Speed Low Power Comparator in ADC
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ABSTRACT: The fast growing electronics industry is pushing towards high speed low power analog to digital converters. Comparator is electronic devices which are mainly used in Analog to Digital converter (ADC). In ADC they are used for quantization process, and are

Differential Non Linearity and Integral Non Linearity Estimation of 4-bit Flash ADC using (CDC)
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Abstract: The Comparator is the vital part of ADC The design of Comparator decides the performance of ADC. The purpose of ADC is to convert Continuous changing input signal into respective digital signal. The input signal varies with time and amplitude so we

A Systematic Design Approach for Low-Power 3-Bit 1 MS/s, 5v MDAC for Pipeline ADC and Design of 6 Bit Pipeline ADC using 3-Bit MDAC
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Abstract The purpose of this work is to design a 3 bit MDAC for a pipeline ADC in a 0.25-µm CMOS technology. The ADC is designed according to thermometer coding. The latched comparator is used to reduce the power consumption. The MDAC designed in this paper

Integration of Sigma Delta ADC with Sine Filter on FPGA
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Abstract: This study presents the architecture of FPGA based Sigma Delta ADC (SD ADC) utilizing higher integration of noise-shaper modulator and a sinc filter. The noise- shaper modulator employed the Low Voltage Differential Signaling (LVDS) as a

A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS-LArg calorimeter readout
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Abstract:This paper presents a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time and allowing a digital calibration, based on a code density analysis, to compensate the capacitors

A Review: High Speed Low Power Flash ADC
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Abstract In computerized world, The Speed, area and power are critical variables for high velocity aplplications. ADC is a mixed signal system that changes over the analog signals to the digital signals for transforming the data. In present day CMOS innovation the flash

LINEARITY ANALYSIS OF SPLIT SAR ADC USING Vcm BASED SWITCHING AND SWITCHBACK SWITCHING FOR WIRELESS SENSOR NETWORK
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ABSTRACT: As advanced CMOS technologies enhance the prepared speed of logic circuit significantly. Successive approximation register (SAR) analog-to-digital converter is wellmatched with the standard CMOS process with low provides voltage, because it does

Design and simulation of low-power ADC using double-tail comparator
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Abstract-Double-tail comparator is basically designed for SAR-ADC in order to optimize the power with which the circuit operates on high-speed. The circuit is designed under 90 nm CMOS technology means by reducing the technology the parameters get also reduced.



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