adc adc analog to digital converter IEEE PAPER 2016
Design of a 10-bit SAR ADC with Enhancement of Linearity on C-DAC Array
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Approximation Register (SAR) Analog to Digital Converter (ADC) reducing device mismatching property driven by MSB node of C-DAC array divided into 4 equal parts. It improves linearity by adding switch for reducing mismatch of MSB node which is the
Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors
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Abstract:This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a samplingtime mismatch as observed in the conventional SHA-free
A 3-bit pseudo-flash ADC for Sensors Interface Circuits
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Abstract A3-bit pseudo flash analog-to-digital converter (ADC) is presented in this paper. For scalability and compactness, the ADC was designed such that only two comparators were required. The complete system design has been implemented in hardware (ie PCB or
Review Paper on the Noise Shaping Property of 4 th order VCO based ADC by using Feedback Loop
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AbstractThis paper presents the review of different order voltage control oscillator analog to digital converter (VCO-ADC) and their SNR calculation. The 4th-order Continuous Time(CT) delta-sigma VCO-ADC has been explored on a 0.13m CMOS with a measured
AN IMPROVE SAR ADC USING REVERSIBLE GATES
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Abstract:Data converters play an important role in an ever-increasing digital world which is dependent on CMOS technology. In CMOS technology, performance degradation of power is one of the foremost questions at daily vitality. The analog to digital converters ADCS are
Building n-bit ADC Using n 1-bit New General ADC Cell Architecture
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Abstract:This work introduces a new general architecture for an analog to digital converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be
VLSI Implementation of ADC Using Aliasing Free Pulse Width Modulation
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Abstract:The Analog to Digital Converters (ADCs) have been in existence for more than 30 years and an integral part of Software Defined Radio, sensor applications and other potential applications. This paper discusses about the implementation of ADC using the
Low Power Design of Asynchronous SAR ADC
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1.2 V has been designed. The schematic diagram of different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. Comparator was designed so that it remains in saturation for proper operation and was implemented using differential
Design of an efficient 8-bit Flash ADC for Optical Communication Receivers
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Abstract:The proposed 8-bit Flash ADC design does not require resistor ladder circuit and it can operate at Giga Hz range with concurrent bubble error correction of 2nd order. It consists of 28 1 comparators and two encoding blocks. First encoding block is a 1 out of
ADC, February 27, 2016, Seattle, WA
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Page 1. + Non-Infectious Catheter/Mechanical Complications Zoe Parr, MD, FRCSC, FACS ADC, February 27, 2016, Seattle, WA Page 2. + OBJECTIVESTo review common catheter complicationsTo review considerations for catheter salvage
Design of Switched Resistor ADC Using VHDL-AMS Tool
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Abstract: This paper presents design and simulation of switched resistor (SR) ADC in analog mixed signal (AMS) environment. The proposed design consists of 1st order single bit SR modulator with dissipated power of 0.935 mW and 2nd order digital decimation
Performance comparison of 3 bit ECRL ADC with conventional logic style
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Abstract:Adiabatic circuits have been one of the preferred designs for reducing overall power dissipation in a circuit. By adiabatic technique, power dissipation in PMOS network can be reduced to optimal rates and some of energy stored at load capacitance can be
Improvement of The ADC Resolution Based on FPGA Implementation of Interpolating Algorithm
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Abstract:This paper exposes a method that gives us the possibility to use a low accuracy Analog-to-Digital Converter (ADC) in high-resolution measurements. We increase the resolution of a 12-bits ADC to 16-bits by adding samples which are calculated using
VLSI IMPLEMENTATION OF 12-BIT SAR ADC OPTIMIZING DYNAMIC POWER
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ABSTRACT Autonomous acoustic-sensor nodes rely on low power circuit techniques to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of a low-power analog to digital converter (ADC). The
Design of a Compact n-bit ADC with Serial Output
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Abstract:This work introduces a novel general design of n-bit analog to digital converter (ADC). It is constructed from one basic ADC cell that generates a digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage
Automated Test Setup for Functional and Parametrical Control of Microcontrollers with InternalADC
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Abstract:the developed automated test setup for microcontrollers with internal analog-to- digital converters is presented. The solution uses PXI-4110 and PXI-7841R modular instruments and LabVIEW software along with individually designed boards. The article
Design of a 1.2-V, 4-Bit Flash ADC Using Sub Threshold CMOS Voltage Reference
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Abstract: In this paper, a 4 bit ADC (Analog to Digital Converter) is designed for low power CMOS. It requires 2-1 comparators and an encoder. This ADC is integrated with proposed subtheshold CMOS voltage reference N which is generated by replacing the analog
Mean ADC values in locally advanced cervical cancer before and after the middle neoadjuvant chemo-radiotherapy treatment: our experience
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Page 1 of 17 Mean ADC values in locally advanced cervical cancer beforePrevious studies have suggested that the mean apparent diffusion coefficient ADC (mADC) may serve as prognostic biomarker of survival and could be used to identify patients at risk for recurrence [4].
Analysis of Integrator for Continuous Time Digital Sigma Delta ADC on Xilinx FPGA
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Abstract:This paper mainly discuss the advantage of CT integrator structure and the design of passive RC integrator for first order continuous time Digital sigma Delta ADC on FPGA. Transient analysis of the passive integrator ie, RC section is carried out and the
DESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTAADC FOR SIGNAL PROCESSING APPLICATION
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Abstract An accurate design of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time Sigma Delta ADC in 180nm CMOS technology using Tanner EDA tools is done. The proposed architecture consists of the loop filter, VCO quantizer
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