cache memory 2016 IEEE PAPER
Average Memory Access Time ReductionVia Adding Victim Cache
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Abstract Memory hierarchy performance, specifically cache memory performance, is an increasingly important factor in the performance of modern computers. Victim caching is an improvement to miss caching by placing a small fully associative cache between a cache
Cache Memory: An Analysis on Performance Issues
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Abstract: Cache Memory is very fast memory placed between CPUMain Memory. Cache memory plays a crucial role in deciding the performance of multi-core systems. In this paper, performance of cache memory is evaluated through following factors cache access time,
Design of a Multi-Threaded Image Signal Processor with a Multi-Bank Cache Memory
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Abstract This paper proposes a multi-thread architecture-based Image Signal Processor (ISP). As the required image quality is gradually increasing in today's society and the image processing algorithms are becoming more diversified, the burden of calculations in the
Achieving high cache hit ratios for CDN memory caches with size-aware admission
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Abstract Content delivery networks (CDNs) allow billions of users to expediently access content with higher reliability and performance from proximal edge caches deployed around the world. Each edge cache typically uses an in-memory Hot Object Cache (HOC)
Code cache management in managed language VMs to reduce memoryconsumption for embedded systems
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Abstract The compiled native code generated by a just-in-time (JIT) compiler in managed language virtual machines (VM) is placed in a region of memory called the code cache. Code cache management (CCM) in a VM is responsible to find and evict methods from the
A generic I/O architecture for data-intensive applications based on in-memorydistributed cache
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Abstract The evolution in scientific computing towards data-intensive applications and the increase of heterogeneity in the computing resources, are exposing new challenges in the I/O layer requirements. We propose a generic I/O architecture for data-intensive
A Survey on Phase Change Memory-Aware Cache Management
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Abstract PCM (phase change memory) has been regarded as one of the most promising NVRAM. Due to its excellent features including high access speed, good scalability, byte addressability, and low idle power, PCM is expected to be an alternative to DRAM or flash
Design Space Exploration of Cache Memory–A Survey
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Abstract:Cache memory plays a major role in memory hierarchy for improving the system performance. Cache configuration includes cache size, associativity, block size, replacement policy and write policies. Selection of different values for all these parameters
Cache Memory Introduction and Analysis of Performance Amongst SRAM and STT-RAM from The Past Decade
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Abstract:The following paper will be an analysis of performances between a variety of cache designs, new and old. We will discuss the basics of cache memory, cache design, and the handling of data amongst the CPU, memory and cache. We will then dwell into
Embedded Systems Dilemma of Chip Memory Diversity by ScratchpadMemory for Cache On-chip Memory
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Abstract:-The aim of this paper is the problem of chip memory selection for computationally intensive applications by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache size are computed using CACTI tools while
Implementation of Cache Designs and Efficiency of Cache Memory
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Abstract:Several cache configurations and cache designs are used in an effort to create an efficient cache memory that bridges the communication between the CPU and main memory. The objective is to discuss different cache configurations or strategies (direct-
Compare The Metrics Between Different Types of Cache Memory from 2005-2016
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Abstract:Technology has been playing a significant role in globalization nowadays. As an engineer, the mission is to improve it every year. The objective of this project is to analyze the improvement by examining the metrics from ten different project papers of the last
Analysis of the Fundamental Metrics of Processor and Cache Memory Over the Past Decade
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The computer technology improves also, especially in the designing of the CPU. By examining the metrics from the ten papers back to the early year 2005 to the present year 2016 that were discussed, the objective of the paper is to analyze the purposes of using
The effects of multilevel cache on CPU and main memory interactions
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Abstract:the focus of this paper is to provide an overview of different cache technology and memory design. The purpose of multi-level cache is to provide the fastest data transfer between the Dynamic RAM with the lowest cost possible. The three main mapping
Technology and Performance Comparison of Cache Design and Memory
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Abstract:Several cache designs and different types of cache configurations are observed to improve and design a cache memory that can help enhance communication between main memory and CPU. The objective is to understand cache latency and energy by studying
Memory-Hierarchy Configurations with Different Cache Technologies from 1995-2016
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Abstract:Cache technologies such as SRAM, STT-RAM, eDRAM ranging from the year 1995-2016 are examined and reviewed. The popular trends happening through the years are highlighted and briefly discussed. An abstract diagram of cache level implementation
MAC: A NOVEL SYSTEMATICALLY MULTILEVEL CACHE REPLACEMENT POLICY FOR PCM MEMORY
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ABSTRACT The rapid development of multi-core system and increase of data-intensive application in recent years call for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size of storage cell. Now further scaling of
Memory Consistency Directed Cache Coherence Protocols for Scalable Multiprocessors
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Abstract The memory consistency model, which formally specifies the behavior of the memory system, is used by programmers to reason about parallel programs. From a hardware design perspective, weaker consistency models permit various optimizations in
Distinction of Modern Cache Configurations: SRAM, STT-RAM, and eDRAMMemory Performance Enhancement with Energy and Design Efficiency Analysis
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Abstract:Modern research has provided insight into many different options of cache design and memory hierarchy. Today's technology has brought about increasing complexity to the cache architecture and several different metrics have been analyzed and argued to be the
cache memory
Dynamic partitioning of shared cache memory
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Abstract. This paper proposes dynamic cache partitioning amongst simultaneously executing processes/ threads. We present a general partitioning scheme that can be applied to set-associative caches. Since memory reference characteristics of processes/threads can change over
Theoretical use of cache memory as a cryptanalytic side-channel.
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Abstract We expand on the idea, proposed by Kelsey et al.[14], of cache memory being used as a side-channel which leaks information during the run of a cryptographic algorithm. By using this side-channel, an attacker may be able to reveal or narrow the possible values of
Cache memory design considerations to support languages with dynamic heap allocation
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Abstract In this report, we consider the design of cache memories to support the execution of languages that make extensive use of a dynamic heap. To get insight into the cache memory design, we define several characteristics of dynamic heap references and measure these
Cache memory optimization to reduce processor/memory traffic
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ABSTRACT--The importance of reducing processor memory bandwidth is recognized in two distinct situations: single board computer systems and microprocessors of the future. Cache memory is investigated as a way to reduce the memory-processor trafct We shovt
High performance memory architectures with dynamic locking cache for real-time systems
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Abstract In modern computers, memory hierarchies play a paramount role in improving the average execution time. However, this fact is not so important in realtime systems, where the worst-case execution time is what matters the most. System designers must use complex
Reducing memory and traffic requirements for scalable directory-basedcache coherence schemes
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Abstract As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of all processors caching a memory block. When a write to that block occurs, pointto-
Tutorial on verification of distributed cache memory protocols
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Page 1. Tutorial on Verification of Distributed CacheMemory Protocols Steven M. German IBM TJ Watson Research Center24 FMCAD Tutorial November 12, 2004 Page 25. Phases in Verification of CacheMemory ProtocolMessage FabricCoherence Protocol
Strategies for cache and local memory management by global program transformation
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Perhaps the most critical feature in the design of a shared memory parallel processor is the organization and the performance of the memory system. Generally, the shared memory is implemented as a set of independant modules which may be themselves interleaved and
Highly efficient LRU implementations for high associativity cache memory
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Abstract-High associativity with replacement policy as LRU is an optimal solution for cache design when miss rate has to be reduced. But when associativity increases, implementing LRU policy becomes complex. As many advance and demanding technologies like
Cache hierarchy and memory subsystem of the AMD Opteron processor
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Recent trends point to high and growing demand for increased compute density in large- scale data centers. Many popular server workloads exhibit abundant processand thread- level parallelism, so benefit directly from additional cores. One approach to exploiting
The cache coherence problem in shared-memory multiprocessors–Hardware solutions
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Abstract Appropriate solution to the well-known cache coherence problem in shared memory multiprocessors is one of the key issues in improving performance and scalability of these systems. Hardware methods are highly convenient because of their transparency for
Implementation issues in modern cache memory
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Abstract| As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, we consider some of the issues that are involved in the
Evaluating effects of cache memory compression on embedded systems
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Abstract Cache memory compression (or compressed caching) was originally developed for desktop and server platforms, but has also attracted interest on embedded systems where memory is generally a scarce resource, and hardware changes bring more costs and
Data cache and direct memory access in programming mediaprocessors
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The most frequently used DMA mode in image computing is the 2D block transfer. When an entire input image does not fit on a chip, the DMA controller transfers the input image from off- to on-chip memory and processes it in small blocks. The 2D block transfer DMA then
Instruction Cache Memory: Issues in Real-time Systems
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Abstract Cache memories can contribute to significant performance advantages due to the gap between CPU and memory speed. They have traditionally been thought of as contributors to unpredictability because the user can not be sure of exactly how much time
Shared tag for MMU and cache memory
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SUMMARY In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To
Cache-conscious concurrency control of main-memory indexes on shared-memory multiprocessor systems
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Abstract Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB+-tree. However, none of these indexes took account of concurrency control,
Toward scalable cache only memory architectures
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Abstract HIGH PERFORMANCE at a low cost is the common goal of most new computers. Even if the speed of microprocessors seems to double every year, there are, and will always be, important applications demanding even better performance. There are two ways of
The SPUR instruction unit: An on-chip instruction cache memory for a high performance VLSI multiprocessor
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ABSTRACT Microprocessor architecture is evolving rapidly as silicon integrated circuits increase in density. On-chip cache memories are becoming an established feature in 32-bit microprocessor designs because they significantly improve performance. Microprocessor
Caching less for better performance: balancing cache size and update cost of flash memory cache in hybrid storage systems.
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Abstract Hybrid storage solutions use NAND flash memory based Solid State Drives (SSDs) as non-volatile cache and traditional Hard Disk Drives (HDDs) as lower level storage. Unlike a typical cache, internally, the flash memory cache is divided into cache space and over-
Implementation of unstructured grid GMRES+ LU-SGS method on shared-memory, cache-based parallel computers
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ABSTRACT The implementation of an unstructured grid matrix-free GMRES+ LU-SGS scheme on shared-memory, cache-based parallel machines is described. A special grid renumbering technique is used for the parallelization rather than the traditional method of
Attacking SMM memory via Intel CPU cache poisoning
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Abstract In this paper we describe novel practical attacks on SMM memory (SMRAM) that exploit CPU caching semantics of Intel-based systems. keywords: CPU Cache, System
Techniques for cache and memory simulation using address reference traces
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Abstract Simulation using address reference traces is one of the primary methods for the performance evaluation of the memory hierarchy of computer systems. In this paper we survey the techniques used in such a simulation. In both the uniprocessor and shared-
Potable Extended Cache Memory to Reduce Web Traffic
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Abstract The Web-based information systems, as the network traffic and slow remote servers can lead to long delays in the answer delivery. Client memory is largely used to cache data and minimize future interaction with the servers. In this paper, we propose an extended
Comparison of cache-and scratch-pad-based memory systems with respect to performance, area and energy consumption
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Abstract In this report we evaluate the options for low power on-chip memories during system design and configuration. Specifically, we compare the use of scratch pad memories with that of cache on the basis of performance, area and energy.target architecture
Sa¥ iag cache memory using a locking cache In real-time systems
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Abstract-Locking cache is a practical alternative to conventional caches in real-time systems, With similar performance than conventional caches, a locking cache allows a simple, accurate schedulability analysis. This work presents a new application of the locking
A Cache Memory System based on a Dynamic/Adaptive Replacement Approach
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Abstract In this work we propose a cache memory system based on an adaptive cache replacement scheme, as part of the virtual memory system of an operating system. We use a sequential discrete-event simulator of a distributed system to compare our approach with
A Taxonomy for Cache Memory Misses
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Abstract-One way to understand the causes of cache memory misses is to use a classification for them. Usually statistical models such as lhe 3C model are used to make the classification. In lhe present work a ncw dcfinition for thc 3C model: compulsory, capacity
Cache Coherence Protocol Design for Active Memory Systems.
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Abstract:Active memory systems improve application cache behavior by either performing data parallel computation in the memory elements or supporting address re-mapping in a specialized memory controller. The former approach allows more than one memory
Bus and cache memory organizations for multiprocessors
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The maximum rate at which data can be transferred over a bus is called the bandwidth of the bus. The bandwidth is usually expressed in bytes or words per second. Since all processors in a multi must access main memory through the bus, its bandwidth tends to limit the
On the Use of Fuzzy Techniques in Cache Memory Managament
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Abstract: Cache memory is integrated into the design of all state-of-the-art computer systems. One of the cache memory management policies is the replacement technique. Conventional replacement procedures include least recently used (LRU), first in first out (
Performance Analysis of On-Chip Cache and Main Memory Compression Systems for High-End Parallel Computers.
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ABSTRACT Cache and memory compression systems have been developed for improving memory system performance of high-performance parallel computers. Cache compression systems can reduce onchip cache miss rate and off-chip memory traffic by storing and
Design verification of the S3. mp cache coherent shared-memory system
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Abstract:This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable Shared-memory MultiProcessor (S3. mp) at three levels of abstraction: the memory consistency model, the cache coherence protocol,
CAMA: Cache-aware memory allocation for WCET analysis
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Abstract:Current WCET analyses do not support dynamic memory allocation. This is mainly due to the unpredictability of cache performance when standard memory allocators are used. We present a novel dynamic memory allocator that makes cache performance
Tsar: a scalable, shared memory, many-cores architecture with global cachecoherence
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The Write-Back policy is generally used in discrete multi-processors architectures, as it saves transactions on the system bus, that is usually the architecture bottleneck, but it is-at least-one order of magnitude more complex than Write-Trough, because any L1 cache
The memory architecture and the cache and memory management unit for the Fairchild CLIPPER Processor
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Abstract The Fairchild CLIPPER is a new high performance three chip module consisting of a microprocessor chip and two cache and memory management (CAMMU) chips, mounted on a small PC board. CLIPPER implements a new instruction set architecture which has
A short study of the addition of an L4 cache memory with interleaved cachehierarchy to multicore architectures
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Abstract In this work, a comparison is made between the performance of a multicore architecture with a large L3 cache and an architecture with an additional cache memory level, L4. It is also proposed an architecture with an interleaved cache hierarchy, for
Task scheduling and memory partitioning for multiprocessor system-on-chip using low-power L2 cache architecture
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ABSTRACT Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter
Towards Reconfigurable Cache Memory for a Multithreaded Processor.
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Abstract Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today, a reconfigurable device can integrate a largescale processor and complex hard-wired logic. System designers
Improving Energy and Performance of Data Cache Architectures by ExploitingMemory Reference Characteristics
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F ollowing the rapid progression and innovation in the semiconductor industry, the microprocessor mar k et is gradually converging into two ma j or segments: The first segment is driven by traditional high-performance microprocessors used in information servers,
Cache-Conscious Index Structures for Main-Memory Databases
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Database index structures have been researched for decades. Disk databases use hard disks as primary non-volatile storage and the main issue is to keep the number of disk operations as low as possible. This is due to the fact that disk access is magnitudes slower
A Performance Study of the DDM: A Cache-only Memory Architecture
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Abstract Large-scale multiprocessors su er from long latencies for remote accesses. Caching is by far the most popular technique for hiding such delays. Caching not only hides the delay, but also decreases the network load. Cache-Only Memory Architectures (COMA
A survey of cache coherence mechanisms in shared memorymultiprocessors
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Abstract This paper is a survey of cache coherence mechanisms in shared memory multiprocessors. Cache coherence is important to insure consistency and performance in scalable multiprocessors. A variety of hardware and software protocols have been
Cache-in-memory: A lower power alternative
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Abstract The concept of Processing-In-Memory PIM achieves many benefits by placing memory and processing logic on the same chip, utilizing more of the available bandwidth and reducing both the power and time associated with memory accesses. Typical
Memory Block Relocation in Cache-Only Memory Multiprocessors.
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Abstract Designed to provide a high utilization of local memory in each processing node, the cache-only memory architecture (COMA) is a type of distributed shared memory multiprocessor, where the local memory serves as a large cache, called attraction memory
Effects of fenitrothion on memory for cache-site locations in black-capped chickadees
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Abstract-The effect of fenitrothion on food caching in the black-capped chickadee was investigated Oral doses of fenitrothion calculated to produce peak brain inhibition levels of 50 to 60% had no effect, or possibly even improved the ability of the birds to retrieve
Fast-Cache: A new abstraction for memory system simulation
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Abstract Trace-driven simulation has long been the dominate technique for evaluating memory system performance. However, the reference trace abstraction, upon which it is based, does not exploit the full potential of on-the-y simulation systems, which tightly
An Integrated Simulation Infrastructure for the Entire Memory Hierarchy:Cache, DRAM, Nonvolatile Memory, and Disk
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As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to
An Abstract State Machine specification and verification of the location consistencymemory model and cache protocol
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Abstract: We use the Abstract State Machine methodology to give formal operational semantics for the Location Consistency memory model and cache protocol. With these formal models, we prove that the cache protocol satisfies the memory model, but in a way
Design and analysis of update-based cache coherence protocols for scalable shared-memory multiprocessors
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Abstract This dissertation examines the performance di erence between invalidate-based and update-based cache coherence protocols for scalable shared-memory multiprocessors. The rst portion of the dissertation reviews cache coherence. First, chapter 1 describes the
Obtaining memory address traces from native co-simulation for data cachemodeling in systemC
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Abstract:Native co-simulation is a fast solution for system modeling at early design stages. In this technique,target processor and, then, it is executed in the workstation combined with a timeapproximate HW platform
Cache conscious data layouting for in-memory databases
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Abstract Many applications with manually implemented data management exhibit a data storage pattern in which semantically related data items are stored closer in memory than unrelated data items. The strong sematic relationship between these data items commonly
Reducing memory bandwidth for chip-multiprocessors using cache injection
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Current and future high-performance systems will be constructed using multi-core chips. These systems impose higher demands to the memory system. Lack of adequate memory bandwidth will limit application performance. To reduce memory bandwidth we propose to
Physical memory forensics for files and cache
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ABSTRACT Physical memory forensics has gained a lot of traction over the past five or six years. While it will never eliminate the need for disk forensics, memory analysis has proven its efficacy during incident response and more traditional forensic investigations. Since
Investigating the Use of Cache as a Local Memory
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Abstract When caches were rst designed, they were very small by today's standards, and the components from which they were constructed were very expensive. For many of today's computer architectures, this is no longer true. Caches have become quite large, some as
Prototyping a configurable cache/scratchpad memory with virtualized user-level RDMA capability
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Abstract. We present the hardware design and implementation of a local memory system for individual processors inside future chip multiprocessors (CMP). Our memory system supports both implicit communication via caches, and explicit communication via directly
Efficient fine grained synchronization support using full/empty tagged sharedmemory and cache coherency
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Abstract Performance results of machines with fine-grain synchronization on individual lock- free data items (eg, words), such as the MIT Alewife multiprocessor, illustrate the benefits of supporting fine-grain synchronization. The performance benefits are primarily the result of
Test data generation for LRU cache-memory testing
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Abstract:System functional testing of microprocessors deals with many assembly programs of given behavior. The paper proposes new constraint-based algorithm of initial cache- memory contents generation for given behavior of assembly program (with cache misses
Efficiently GPU-Accelerating Long Kernel Convolutions in 3-D DIRECT TOF PET Reconstruction via Memory Cache Optimization
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Time-of-Flight (TOF) PET reconstruction. Its novelty stems from the fact that it performs all iterative predictor-corrector operations directly in image space. The projection operations now amount to convolutions in image space, using long TOF (resolution) kernels. While
Cache Memory: An Analysis on Optimization Techniques
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Abstract:Processor speed is increasing at a very fast rate comparing to the access latency of the main memory. The effect of this gap can be reduced by using cache memory in an efficient manner. This paper will discuss how to improve the performance of cache based CSE PROJECTS