ENGINEERING RESEARCH PAPERS

cmos vlsi 2016 IEEE PAPER




Optimization of Control Block of 3-bit PWM using Adiabatic Dynamic CMOSLogic for OLED Illumination System Based on Internet of Things Service
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Abstract The environment development for deep sleep has been studied using analysis results of the big data about vital signs and parameters in the bedroom. The organic light emitting diode (OLED) illuminations of the bedroom are dimming using analysis results of

200-GHz CMOS amplifier with 9-dB noise figure for atmospheric remote sensing
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The feasibility of using CMOS technology for RF amplification in atmospheric remote sensing receiver is studied. The design and measurement results of a 200-GHz low-noise amplifier which is fabricated using a 32-nm SOI CMOS technology are presented. The 8-

CMOS High-Throughput Electrophysiology System to Analyze Neurons at Subcellular and Network Levels
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METHODS: The HDMEA, as depicted in Fig. 1, features an active sensing area of mm2 hosting 26'400 platinum microelectrodes. The electrodes are arranged in a grid-like configuration with a center-to-center pitch of yielding an electrode density of

Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method
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ABSTRACT Reducing the power consumed by the device is the emerging trend now-a-days. The aim is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power

A Portable, Low-cost System for Optical Explosive Detection based on a CMOSCamera
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Abstract: Humanitarian demining requires a variety of methods and instrumentation for effective mine clearance, since a wide range of materials are used in mine manufacturing. However, landmines release vapours over time that can be detected, for example, by

Advances in Capturing Child Fingerprints: A High Resolution CMOS Image Sensor with SLDR Method1
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Abstract: The use of biometrics technology for person identification has become prevalent due to several innovations as a result of research and development in this field. The purpose of this study is to find a solution which realizes newborn and infant (younger than 12

CMOS-compatible photonic devices for single-photon generation
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Abstract: Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the

A CMOS Full-Cycle Mixing Vector Modulator
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Abstract:This letter presents a new vector modulator architecture which makes full use of the baseband signals when performing signal mixing to enhance the already improved conversion gain of the mixers which use the local oscillator signals (LOs) of 25-percent

Study and Review on VLSI Design Methodologies and Limitations using CMOSAdder Circuits
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ABSTRACT In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power

A Comparative Study of Static and Dynamic CMOS Logic
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Abstract The choice of the CMOS logic to be used for implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. Several design options exist for CMOS combinational gates. One

K-Band Single-Path Dual-Mode CMOS Transmitter for FMCW/UWB Radar
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Abstract:A K-band dual-mode radar transmitter is imple-mented with 0.13-µm CMOS technology, which supports both FMCW and UWB radar operations. A dual-functional block is proposed to achieve efficient dual-mode operation without additional paths and

An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOSTechnology
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Abstract Robust, high performance oscillator design in CMOS technology continues to pose interesting challenges. CMOS circuitry in VLSI dissipates less power during static, and is denser than any other implementations having the similar functionality. This paper

Nonvolatile Online CMOS Trimming with Magnetic Tunnel Junctions
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ABSTRACT We design a programmable output delay for digital circuits, making use of the nonvolatile bit storage in magnetic tunnel junctions (MTJs), which are available in hybrid processes with CMOS. We introduce our programmable clock buffers in VLSI dot product

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 CMOS
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Abstract:This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and

Design of RF CMOS Transceiver for Wireless Data Communication of Three-Dimensional Integrated Circuit Applications
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Abstract In this study, a wireless type of chip-to-chip communication (WCC) technology is proposed as the next generation of three-dimensional (3D) semiconductor technology. To demonstrate the feasibility of the technology, we design a transceiver and receiver for

Charge-based CMOS Digital RF Transmitters
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The point where wireless communication and ubiquitous connectivity became an essential part of our lives is already past. Generation after generation communication speed is being taken to unprecedented levels, requiring both state-of-the-art hardware and software to

A Robust, Low Distortion CMOS Current Driver Circuit For Wideband Frequencies
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Abstract-Multi frequency Electrical Bio-impedance (MEB) has been widely used as non invasive technique for characterizing tissue. Most MEB systems use wide band current sources for injecting current and instrumentation amplifiers for measuring resultant

Design of a Miniature CMOS APS Star Tracker
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Abstract:Star trackers are currently the most advanced attitude measuring instruments. They have the advantages of high precision, small quality, no drift, strong antiinterference and autonomous navigation without relying on other navigation systems. This paper

'Junction-Level'Heterogeneous Integration of III-V Materials with Si CMOS for Novel Asymmetric Field-Effect Transistors
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The silicon Complementary Metal-Oxide-Semiconductor (Si CMOS) technologies have been the mainstream in semiconductor IC industry for the past few decades. These transistors act as ideal voltage-controlled switches in digital logic applications and amplifiers in analog/

Design and Analysis of 32 bit SRAM architecture in 90nm CMOS Technology
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Abstract-In this paper, 32 bit SRAM Architecture design using 90nm CMOS technology has been proposed. The SRAM architecture includes 6T Memory cell, precharge circuit, write driver, address decoder, sense amplifier respectively. Total power dissipation of 195.81

Characterization of embedded Micro-heater and Temperature Sensor in aCMOS-MEMS Resonator for gas sensing
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Abstract-In this paper, a CMOS-MEMS resonator is fabricated with embedded micro-heater and temperature sensor for application in the detection of ammonia in exhaled breath. The resonator is fabricated using commercial 0.35 µm CMOS technology. An aluminium micro-

Design of 64-bit hybrid carry select adder using CMOS 32nm Technology
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Abstract-This paper presents low leakage carry select adder (CSA). CSA is one of the fastest adders used in many data-processing systems to perform fast arithmetic operations. In this paper Carry Select Adder uses single RCA and binary to excess-1 converter (BEC) are

Implementation of Broad band and Zero Distortion CMOS Current Driver Circuit for Bio-medical Applications
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ABSTRACT Multi frequency Electrical Bio-impedance has been widely used as noninvasive technique for characterizing tissue. Most systems use wide band current sources for injecting current and instrumentation amplifiers for measuring resultant potential

Automated Resonance Matching for CMOS MEMS Micro-resonators
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Abstract:This paper reports the design and characterization of a phase-locked loop-based control scheme implemented in a complementary metal–oxide–semiconductor process for resonance matching between capacitive micro-resonators. The system-on-chip

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
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Abstract:To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional

Effect of RC Compensation on Switching Regulation of CMOS Low Dropout Regulator
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Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate

AC and Transient Analysis of N Type Carbon Nanotube Based cum CMOSbased Folded Cascode Operational Amplifier
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Abstract:Carbon Nanotube Field Effect Transistor (CNTFET) will play vital role in designing of combinational and sequential circuits which are back bone of digital computers. It is clear that carbon nanotube field effect transistors are the future of electronic circuit. This paper

High Speed and Low Power CAM Based on CMOS Technology
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Abstract: Ternary Content Addressable Memory (TCAM) is a high performance search engine, which access the data based on its contents in a single clock cycle. To overcome this drawback we need to reduce the power consumption of the TCAM when we search

Theoretical and Experimental Investigations of Thermoresistive Micro Calorimetric Flow Sensors Fabricated by CMOS MEMS Technology
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Abstract:A general 1-D model was presented to predict the characteristics of CMOS thermoresistive micro calorimetric flow (TMCF) sensor with two types of packaging, ie, open- space type and channel type, for both gases and liquids. The 1-D model was first

Reliability-Aware Design Method for CMOS Circuits
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Abstract:In this paper a reliability-aware design method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. Within this

Denoising Algorithm for the Pixel-Response Non-Uniformity Correction of a Scientific CMOS Under Low Light Conditions
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ABSTRACT: We present a denoising algorithm for the pixel-response non-uniformity correction of a scientific complementary metal–oxide–semiconductor (CMOS) image sensor, which captures images under extremely low-light conditions. By analyzing the integrating

Analysis and Design of Low Power All Digital Phase Locked Loop via Dynamic Logic-Phase Frequency Detector in a Standard 0.25-um CMOS Technology
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Abstract: A low power design of All Digital Phase Locked Loop (ADPLL) have become more attractive. It has better programmability, testability, portability and stability on ADPLL various actions and has good noise immunity. All digital system clock generation digital phase

Study of Threshold Gate And CMOS Logic Style Based Full Adder Circuits
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Abstract:In this review paper different design techniques of 1-bit full adder are deliberate using linear threshold logic gates (LTLG). The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power

Material selection for CMOS compatible high Q and high frequency MEMS disk resonator using Ashby approach.
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Abstract In this paper, the most appropriate material for MEMS Disk resonator compatible with CMOS technology is selected using the Ashby approach. Materials indices are formulated based on three primary performance parameters, namely high Q, high

Design and Analysis of Low POWR Class AB Two Stage Op-Amp with CMOSTechnology
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Abstract: The operational amplifier is perhaps the most useful integrated device in existence today. We introduced various class AB two stage op-amps with high and approximately symmetrical slew rate and very simple architecture are introduced. A combination of

Implementation and Comparison of Power Gated CMOS Circuits
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Abstract-As CMOS technology scales down, supply voltage is reduced to avoid device failure. This decreases the switching speed of transistors. To prevent this speed problem, threshold voltages of the transistors are reduced, due to which sub threshold leakage

Numerical Simulation of Packaging Effect on the CMOS MEMS Calorimetric Flow Sensor
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To achieve a well functionalized flow measurement system, considerable work in the packaging of thermal flow sensors is needed. To reduce the costly chip size in the CMOS process, the employment of housing structure is a practical solution. Previously, we

Low Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nmCMOS Technology
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Abstract Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get

A design of HTM spatial pooler for face recognition using Memristor-CMOShybrid circuits
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Abstract:Hierarchical Temporal Memory (HTM) is a machine learning algorithm that is inspired from the working principles of the neocortex, capable of learning, inference, and prediction for bit-encoded inputs. Spatial pooler is an integral part of HTM that is capable

A Survey on Energy Efficient CMOS Arithmetic Circuits
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Abstract: Energy efficiency is one of the most required features for modern electronic systems and those portable electronic devices demands the availability of low-power building blocks that enable the implementation of long-lasting battery-operated systems.

High-Ratio Voltage Conversion in CMOS for Efficient Mains-Connected Standby
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The focus of this work can be seen as making the bridge between the fields of Solid-State Integrated Circuits (IC) and Power Electronics. Multiple AC-DC and DC–DC power converters are investigated from the IC standpoint, this means a constant effort to realize

Variation-Aware Advanced CMOS Devices and SRAM
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There is no doubt that advanced silicon integrated circuit (IC) technology has thoroughly changed the way we live. Human life has become much more convenient since hand-held mobile electronic devices were developed. This new era, called the era of the hyper-

Design Ratio-Memory Cellular Neural Network (RMCNN) in CMOS Circuit Used in Association-Memory Applications for 0.25 mm Silicon Technology
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Abstract: The paper is proposed the Ratio-Memory Cellular Neural Network (RMCNN) that structure with the self-feedback and the modified Hebbian learning algorithm. The learnable RMCNN architecture was designed and realized in CMOS technology for associative

LVPLL with MCSS Charge Pump in 90nm CMOS for SoCs
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Abstract-A Low voltage Power Efficient Phase Locked Loop is designed for SoCs. A MCSS Charge Pump is introduced to reduce leakage current and current mismatch. In order to achieve wide tuning range at low VCO gain Kvco. A Low voltage VCO (LV-VCO) for low

CMOS Circuits and Systems for Lab-on-a-Chip Applications
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Abstract Complementary metal oxide semiconductor (CMOS) technology allows the functional integration of sensors, signal conditioning, processing circuits and development of fully electronic integrated lab-on-a-chip. On the other hand, lab-on-a-chip is a

Design of CMOS programmable output binary and fibonacci switched capacitor step-down DC-DC converter
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Abstract:This paper describes the CMOS implementation of an open-loop variable output voltage switarget voltages.target voltages generated using n-flying capacitors are of the

Radon Detection using a CMOS Alpha Sensor
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Abstract A radon monitor based on a 3 mm× 3 mm alpha particle-detecting IC fabricated in a foundry CMOS process is reported. The alpha-detecting IC consists of a 16× 16 array of pn junction diodes (sense diodes) that are precharged in reverse bias and then allowed to

Study of V/Q Non-Linearity in Scientific CMOS Sensor
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Abstract Scientific CMOS sensor usually manifests V/Q non-linearity in charge-to-voltage conversion. Starting from the mechanism underlying this non-linearity, we build the V/Q non- linearity model to study the influence of modulation transfer function (MTF) and signal-to-

Ultra-low-power and Ultra-low-cost Short-range Wireless Receivers in Nanoscale CMOS
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With the continued maturation of the Internet of things (IoT) for smart cities, a huge market has been opening up for short-range wireless communications, especially for ubiquitous wireless sensor networks (WSNs). It is expected that by 2020, the IoT market will be close

Universal Filter Design using 45nm CMOS-based DDCC for Bluetooth/Zigbee Applications
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ABSTRACT The limited performance of voltage mode Op-amps such as bandwidth, slew- rate etc. led the analog designer to search for other possibilities and other building blocks. Thus the currentmode active building blocks received considerable attention due to their

CMOS RF Circuit Design for Reliability and Variability
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It is well known that wireless transceivers are implemented in mobile devices such as smart phones, laptops, tablets, etc. Wireless transceivers are also critical circuit blocks for sensors in the Internet of Things (IoT) era. IoT is being represented as a worldwide network

Design Of Cmos 1k Bit Sram Cell Using Cadence 180 Nm Technology
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Abstract: In today's technological environment, there is a huge demand for devices with low power and low cost storage space. Memories with low power are driving the entire VLSI industry mainly because most of the devices work on remote power supply. Demand of

Active Inductor Designs for RF CMOS Receiver Front-End
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Abstract Inductors are a necessary building block in many circuits, including LNA and oscillators largely used in Receivers and various other systems. Because planer inductors can occupy a large amount of area in integrated-circuit (IC) designs, the search has been

Self-Cascode Structures Using Optional devices in Standard CMOS Technology
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Abstract-This paper describes two possible configurations of an asymmetric-VTH self- cascode (SC) structure using optional devices in a 0.18-µm standard CMOS process. Standard CMOS technologies offer optional devices for a range of circuit design solutions,

A 30–75 dB 2.5 GHz 0.13-µm CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication
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Abstract:This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-µm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-PerformanceCMOS Image Sensors
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Abstract:This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a samplingtime mismatch as observed in the conventional SHA-free

CMOS 2-port Active Inductor using LC Resonance Circuit
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Abstract-This paper presents a novel 2-port high-Q active inductor using LC parallel resonator. The proposed 2-port high-Q active inductor consists of the feedback parallel resonance circuits that comprise of low-Q spiral inductor and capacitor. The novelty of the

Modeling and Design of EMI-Immune OpAmps in 0.18-µm CMOS Technology
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Miller-based operational amplifier structures that are highly immune to electromagnetic interference (EMI). The proposed CMOS Miller-based operational amplifier is derived using the present modeling. It provides higher immunity to EMI that is injected into the amplifier's

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage
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In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due

Design of 24GHz Down-Conversion CMOS Mixer
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Abstract This paper presents 24GHz down-conversion CMOS mixer for automotive collision avoidance radar. This circuit operates at the operation frequency of 24GHz, and it contains Gilbertcell type. The proposed circuit is also implemented using TSMC 0.13 µm mixed

A 600 GHz Varactor Doubler using CMOS 65nm process
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Abstract-Varactor and active mode doublers are fabricated and compared in 600 GHz frequency range in terms of output power using CMOS 65nm technology. In designing a frequency multiplier, active mode is generally preferred, since it can provide high

Low Noise Integrated CMOS Direct Conversion RF Receiver Front-End
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For RF Narrowband applications, there are three possible RF receiver architectures: high-IF, low-IF and zero-IF. A zero-IF receiver has also been referred as a homodyne or direct conversion receiver (DCR) and has attracted a lot of attention lately because of possibility

Small-Swing Cross-Coupled Inverters Based Low-Power Embedded Memory in Logic CMOS Technology
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Abstract This paper describes an innovative low-power embedded memory utilizing small- voltage swing logic CMOS bit-cell. The memory cells are composed of two cross-coupled inverters without any access devices. The sources of PMOS transistors are connected to

CMOS indoor light energy harvesting system for wireless sensing applications
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This book presents a micro-power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si: H PV) cells, processed by a switched-capacitor (SC) voltage doubler circuit with maximum power point tracking (

Design and Analysis of Low Power Frequency Synthesizer Circuit Using PLL and Phase Discriminator with 50nm CMOS Technology
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Abstract: Phase locked loop (PLL) is widely applied for different purposes in various domains such as communication and instrumentation. In the microwave range they have been applied in frequency synthesis and phase recovering among others. Phase-locked

Reliability Issues and Design Solutions in Advanced CMOS Design
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ABSTRACT Over decades, scientists have been scaling devices to increasingly smaller feature sizes for ever better performance of complementary metal-oxide semiconductor (CMOS) technology to meet requirements on speed, complexity, circuit density, power

ANFIS AND BPNN BASED POWER ESTIMATION METHOD FOR CMOS VLSI CIRCUITS
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Newer advancement in VLSI technology has led to integration of large number of transistors in a single chip and complexity of the circuits increases rapidly so that the power estimation became vital task at this stage. This work presents an Adaptive Neuro Fuzzy Inference

Design rules of the CMOS inverter for voltage converters
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Abstract:This paper presents a description of the dominantcharacteristics of the CMOS inverter, which is used for voltage converters–charge pumps applications. This circuit controls transport charge between main capacitors to create a higher DC voltage. The

A Fully Integrated CMOS Precision Full-Wave Rectifier
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Abstract This paper presents a new fully integrated high frequency precision full-wave rectifier, which is highly suitable for CMOS technology implementation. The structure comprises a voltage-to-current converter, current rectifiers and a currentto-voltage

DESIGN AND IMPLEMENTATION OF 60 GHZ CMOS POWER AMPLIFIERS
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Page 1. DESIGN AND IMPLEMENTATION OF 60 GHZ CMOS POWER AMPLIFIERS by challenge in the development of 60 GHz wireless transceivers, especially if CMOS technology is chosen for implementation of fully integrated 60 GHz wireless systems.

Implementation And Evaluation Of SAT-based Attacks On Hybrid STT-CMOSCircuits For Reverse Engineering
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With the rapid advancement in semiconductor technology due to the phenomenon of technology scaling, the device dimensions in the integrated circuits (ICs) have been reducing leading to the device integration density doubling every two years, in

Design of CMOS Based Numerical Control Oscillator with Better Performance Parameter in 45nm CMOS Process
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Abstract Numerically Controlled Oscillator (NCO) is an important component in many Digital Communication Systems such as Digital Radio and Modems, Software Defined Radios, Digital Down/Up converters for Cellular and PCS base stations etc. This work presents a

High-Precision CMOS Analog Computational Circuits Based on a New Linearly Tunable OTA
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Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed

The Effects of BTI Aging on the susceptibility of On-Chip Communication Schemes to Soft Errors in Nano-Scale CMOS Technologies
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Abstract. The continuous scaling of semiconductor devices has introduced new circuit failure mechanisms such as bias temperature instability, and made existing reliability problems more severe such as single event transients (SET), variability and crosstalk. This work

Accurate Characterization Method for Cross-Line on CMOS Based on Two-Port Measurements
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VLSI IMPLEMENTATION OF CMOS ANALOG MULTIPLIER
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Abstract-A new CMOS voltage-mode four-quadrant analog multiplier is proposed and analysed. It is a VLSI based low voltage low power CMOS four quadrant analog multiplier. MOSFETs in the circuit used are in the strongly inversion saturated mode. The circuit uses

A Low Noise Two Stage Operational Amplifier on 45nm CMOS Process
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Abstract–A new low voltage and low power two stage operational amplifier which describes different parameters as Gain, Phase margin, Noise, SFDR and THD under 45nm CMOS technology. Implementations have been done in Tanner EDA software V14. 1. Circuit

Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology
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A precision voltage reference circuit is an important component of analog/mixed-signal (AMS) systems. It provides a DC output that is used in various other system components, such as bias networks and data converters. When designing a voltage reference, the

Low-Power Techniques for CMOS Wireline Receivers
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The push for higher data rates in copper media continues unabated. The use of fewer lanes to carry faster data is attractive, especially if the power dissipation per lane can be maintained relatively constant. In the limit, most of the transceiver power is dissipated in

REACTIVE REJUVENATION OF CMOS LOGIC PATHS USING SELF-ACTIVATING VOLTAGE DOMAINS
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ABSTRACT Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, power-gating has been utilized as an effective low-power design technique which has

A low-power 10-bit continuoustime CMOS A/D converter
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ABSTRACT This paper presents the design of a third order low-pass S analogto-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm- C integrators, where the transconductors are implemented using CMOS

Data acquisition development and background studies for the space borne detector AMS-02 and the CMOS detector MIMOSA-V
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This thesis deals with the development of particle detectors as well as the analysis of their responses and simulations of physical interactions inside of them. The covered detector designs reach from a large scale multi purpose detector with several sub-detectors for

Avalanche Photodiode Fabricated in Standard 0.35 µm CMOS Process
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Abstract We present a structure and equivalent circuit model of avalanche photodidode with standard 0.35-µm complementary metal-oxide-semiconductor (CMOS) technology. Measurements demonstrate that this structure offers a high dynamic responsivity and a

Dynamic circuits for CMOS and BICMOS low power VLSI Design
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Abstract:Today, in dynamic circuit's logic gates are used in CMOS and BICMOS technologies by using diodes, resistance and capacitors to decrease the swing in the voltage at output end. This technique improves both power dissipation and delay by using

Fine-Grained 3-D CMOS Concept using Stacked Horizontal Nanowire
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Abstract:To continue miniaturization of Integrated Circuits (IC), 3-D CMOS approaches using layer-layer, die-die and wafer-wafer stacking were proposed. Although these approaches achieve incremental density benefits compared to 2-D CMOS, they exhibit