ENGINEERING RESEARCH PAPERS

vlsi research papers 2015 IEEE PAPER



VLSI IMPLEMENTATION OF INTEGER DCT ARCHITECTURES FOR HEVC IN FPGA TECHNOLOGY
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Abstract: High Efficiency Video Coding (HEVC) inverse transform for residual coding uses 2-D 4x4 to 32x32 transforms with higher precision as compared to H. 264/AVC's 4x4

CMOS LEVEL SHIFTERS
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On-die voltage regulation leading to power 'islands' that can have different voltage levels. Power management that shuts functional units off. Voltage-Frequency pairs; CPU's can be run in several operating points where its power supply is adjusted to reduce power: – lowest

IC Layout Design of Decoder Using Electric VLSI Design System
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Circuit (IC) layout for a decoder. The layout was designed by using an open source software namely Electric VLSI Design System as the Electronic Design Automation (EDA) tool. In order to produce the layout, the basic knowledge of fabrication process and IC design

VLSI Implementation of Low Power FIR Filter Design Using APC-OMS Algorithm
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Abstract: Memory based structures are used in many kind of digital signal processing (DSP) application. Memory-based structures are better performance In area minimization compare with multiply-accumulate structures and have many other advantages like reduced latency

MINIMIZATION OF VLSI FLOORPLAN USING HYBRID CUCKOO SEARCH AND PSO
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Abstract:-Floorplanning is a major issue in the very large-scale integrated (VLSI) circuit design automation. It helps to determine the size, reliability, performance and area of the chip.target of VLSI floorplanning is to minimize both area and wire length Aggressive scaling of semiconductor process technology over the last several decades has resulted in creation of many new products, such as computers, camera, cell phones, and information appliances. This trend is expected to continue for the coming years and create Interconnect has become a crucial element in advanced electronic systems. State-ofthe-art CMOS processes utilize 10 or more layers of metal above the active transistors, so these interconnect layers dominate processing costs. In recent years, interconnect power and

Design of efficient VLSI arithmetic circuits
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Abstract Arithmetic and Logic Unit (ALU) is a critical component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required

Multi Objective Particle Swarm Optimization based Mixed Size Module Placement in VLSICircuit Design
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Abstract: Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. Placement algorithms try to minimize the longest delay along the paths in the circuit

A Study on Power Distribution in VLSI
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ABSTRACT Low power has emerged as a principal theme in today's world of natural philosophy industries. Power dissipation has become a crucial thought as performance and space for VLSI Chip style. With shrinking technology reducing power consumption and

A VLSI Implementation of High Sensitive Fingerprint Sensor using Parasitic Insensitive Charge Transfer Circuit
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Abstract This paper implements 80x64 array high sensitive fingerprint sensor with the parasitic insensitive charge transfer circuit. The fingerprint sensor cell uses an active output voltage feedback integrator. The parasitic insensitive charge transfer circuit includes a

A Scalable VLSI Architecture for Real-Time and Energy-Efficient Sparse Approximation in Compressive Sensing Systems
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In recent years, compressive sensing (CS) has attracted great research attention in fields of applied mathematics, computer science, and electrical engineering. CS theory is established on the fundamental fact that most natural signals are highly compressible

A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit
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(WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high- speed. The w-cell which is suitable for VLSI implementation consists of only four

VLSI Based Image Scaling Application for Raw Images By Using A Novel Video Stream Scaler Technique
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ABSTRACT In this paper a video stream scaler technique is used for image scaling application. The anticipated image scaling algorithm consists of Ram FIFO (RFIFO), RAM fill logic, Read control and blend control. The video stream scaler performs resizing of video

LOW POWER AND TEST DATA COMPRESSION IN VLSI TESTING USING NEW ENCODING SCHEME
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Abstract-Power dissipation during test is a significant problem as the size and complexity of systems-on-chip (SOCs) continue to grow. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation. This problem is

A VLSI Architecture for H. 264/AVC Variable Block Size Motion Estimation
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Abstract:In this paper, we propose an efficient VLSI architecture for variable block size motion estimation (VBSME) in H. 264/AVC to reduce the hardware cost and latency. The proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of

EE-382M VLSI–II OFF-CHIP DRIVERS/RECEIVER DESIGN SPRING 2015
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Send 1's and 0's chip to chip Can it be accomplished with simple inverters Transmit data at the highest frequency with minimal errors. Chip to chip transfers controlled by common

EE-382M VLSI–II FLIP-FLOPS Spring 2015
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Consequences – Increased flip-flop overhead Cycle time in 12 to 15 stage pipeline micro-Architectures is about ~22 FO4 delays FLOP overhead ~3 FO4 delay (DQ delay)

VLSI Implementation of 4X4 MIMO SC-FDMA Transceiver for Low Power Applications
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Abstract Single Carrier-Frequency Division Multiple Access (SC-FDMA) is an OFDMA alternative technology. SC-FDMA is the multiuser version of single carrier modulation with frequency domain equalization (SC/FDE). The main objective of SC-FDMA is to introduce

Reduced Clock Allocation Network for On-Chip Compression Format in VLSI Design
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Abstract: Now-a-days power dissipation is a vital subject in elevated presentation digital routes, because the amount of transistors has increased significantly. Several methods have been planned to decrease the switching activity. This paper presents a new examination

VLSI Routing for Advanced Technology
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VLSI 1 design is the process of creating construction plans for complex integrated circuits, commonly known as chips, which contain up to billions of transistors. Due to its high complexity, this process is divided into several steps, each of them comprising hard

VLSI DESIGN OF LMS ADAPTIVE FIR FILTER FOR HIGH SPEED APPLICATION
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Abstract:In this paper, we show an effective design for the implementation of a delayed least mean square adaptive filter and low power reconfigurable finite impulse response filter for achieving lower adaptationdelay and area-delay-power efficient implementation. we

VLSI IMPLEMENTATION OF NXN PARALLEL DECIMAL MULTIPLIER USING CSA
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Abstract: This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry save multi operand addition that uses a novel BC 4221 recoding for decimal digits. It significantly improves the area and

VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM
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Abstract A novel implementation of code based cryptography (Cryptocoding) technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size

VLSI Implementation of Neural Network
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Abstract:This paper proposes a novel approach for an optimal multi-objective optimization for VLSI implementation of Artificial Neural Network (ANN) which is area-power-speed efficient and has high degree of accuracy and dynamic range. A VLSI implementation of

Low-Complexity and Power Efficient VLSI Architecture for Turbo Decoder
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Abstract: Turbo codes consumes less power consumption and are powerful error correcting code, hence utilized in power constrained wireless communication applications. In this work, implementation of turbo decoder is considered to reduce the area, delay and power using

A Review on Memristor MOS Content Addressable Memory (MCAM) Design Using 22nm VLSITechnology
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Abstract-Large capacity content addressable memory (CAM) is a key element in wide variety of applications. A major challenge in realization of such systems is the complexities of scaling MOS transistors. Converges of different technologies, which are well-matched with

common bus principle is presented. Problems are studied which arise in the impLementation of this. concept by means of s-elf-synchronizing (aperiodic) VLSI.
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Implementation of the protocols of interconnection of entities at the bottom, physical layer of network architecture [l] has a number of peculiar features. In contrast to the general requirements to protocols of higher layers, it requires a more detailed study of certain

Implementation on Low Power Design Using Comparator for VLSI Design Circuit
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ABSTRACT: A 8-bit 5GS/s streak simple to-advanced converter (ADC) is composed and reproduced in a 0.18 CMOS innovation. Low-swing operation both in the simple and the computerized hardware brings about fast low power operation. The ADC disperses 30mW

High Throughput and Efficient VLSI Architecture for Speech Enhancement
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Abstract: This paper presents the implementation of high through-put hardware architecture for enhancing speech using spectral subtraction algorithm. Using the spectral subtraction algorithm the input speech is made free from the effect of background noise. This is done

AN ASYNCHRONOUS LOW POWER AND HIGH PERFORMANCE VLSI ARCHITECTURE FOR VITERBI DECODER IMPLEMENTED WITH QUASI DELAY
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Abstract: Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of

VLSI Implementation of Reversible Binary Adders in Quantum-Dot Cellular Automata
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ABSTRACT: Nowadays exponential advancement in reversible computation has lead to better fabrication and integration process. It has become very popular over the last few years since reversible logic circuits dramatically reduce energy loss. It consumes less power by

VLSI Implementation of Split-Radix Fast Fourier Transform: ASurvey
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Abstract: The purpose of a transform is to consider an algorithm or a fixed procedure or a set of rules or anyequation that changes one set of data to another set of data. The Fast Fourier Transform which is an efficient way to calculate the Discrete Fourier Transform produces

VLSI Implementation of Back Pr for Signal Proc
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Abstract-Mainly due to the rapid advances in integra technologies, large-scale systems design-in short, due to advent of VLSI Technology, the number of applications integrated circuits in high-performance comput telecommunications, and consumer electronics has

Disadvantages of High Power Integrated Circuits and Requirements of VLSI ICs with Low Power Consumption
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Abstract-In this paper, disadvantages of high power consumption and requirements of low power design are discussed. Today, all the portable devices need to be realized with low power architectures because of power consumption is a main consideration along with

NEW VLSI BWA ARCHITECTURE FOR FINDING THE FIRST W MAXIMUM/MINIMUM VALUES USING SORTING ALGORITHMS
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Abstract: Low density parity check (LDPC) codes have been extensively adopted in next- generation forward error correction applications because they achieve very good performance using the iterative decoding approach of the belief-propagation (BP). The

Neuromorphic VLSI Implementation of Analog Inner Hair Cell and Auditory Nerve IC Using Non-Invasive Technique
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Abstract:An analog inner hair cell and auditory nerve IC has been implemented using noninvasive techniques. Differential topology is used to remove the reverberations caused. A fully-differential current-mode architecture is used and the ability to correct channel mismatch is evaluated

Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design
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Abstract:The demand for portable consumer electronics products is increasing at extremely high rate in recent years; therefore development of low-power VLSI circuits is essential. To achieve this objective a lot of innovative work has been done in this field, many innovative

Area–Efficient VLSI Implementation for Parallel Linear-Phase FIR digital Filters
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Abstract The fast finite-impulse response (FIR) algorithms (FFAs), able to create a new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The

VLSI based Fuzzy Logic Static Voltage Regulation System
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Abstract: Fixed Voltage Regulator is an electronic device that regulates changeable voltages in a specific approach and protects the apparatus through practically eliminating any transients in the sharing set of connections. It is a good number appropriate for24-hour

ERROR DETECTION AND CORRECTION USING HAMMING CODE IN VLSI DESIGN UNDER NUCLEAR ENVIRONMENT
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Abstract: Errors occur in VLSI circuits which are deployed in nuclear power plants due to radiation, temperature changes etc. Reliability is a major concern in advanced electronic circuits. Errors caused for example by radiation become more common as technology

VLSI IMPLEMENTATION OF A PROGRAMMABLE LOW DROP-OUT VOLTAGE REGULATOR
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Abstract LDO voltage regulators compose a small subset of the power supply arena. Low- drop-out (LDO) voltage regulators are used in analog applications that generally require low noise and high accuracy power rails. Voltage regulators provide a constant voltage supply

Performance Analysis of Boostable Repeater in Different VLSI Interconnects and Applications
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Abstract: In the era of Nanometer technology variation of process aging of circuits cause vulnerable to establish circuits with the characteristics of adapting themselves and thereby a chance to compensate changes with the proposed one. Aging of circuitry and variations in

Fully Reused VLSI Architecture of FM0/Manchester Encoding for DSRC Applications by Using SOLS Technique
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(DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dc-balance, enhancing the signal reliability. Nevertheless, the coding-diversity between the FM0 and

VLSI Designs for Low Power Applications
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Abstract:Low power has emerged as a principal theme in today's world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With shrinking technology reducing power consumption and

Performance Enhancement of VLSI Circuits using CNTFETs
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Abstract:: In the world of integrated circuits, CMOS has lost it's credential during scaling beyond 32nm. The main drawbacks of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are

VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS
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ABSTRACT As technology trends advances workstation chips become increasingly parallel, an efficient communication substrate is decisive for meeting performance and energy targets, also as nanometre technology shrinks day by day work station chips migrated to

A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design
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Abstract: A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely

SAF ANALYSES OF ANALOG AND MIXED SIGNAL VLSI CIRCUIT: DIGITAL TO ANALOG CONVERTER
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ABSTRACT Digital to analog converter is widely used mixed-signal circuit. Testing of analog and mixed signals faces lots of challenges due to the wide range of circuits and unavailability of one appropriate fault model. SAF (stuck_at_Fault), Stuck_open and

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Abstract:Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

Design and comparative study of a fast N-bit divider and its VLSI Implementation
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Abstract:The design of a fast divider is an important issue in high-speed computing. Instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial

VLSI implementation of modified Booth Algorithm
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Algorithm using 0.5 um CMOS technology. Booth Algorithm allows for smaller, faster multiplication circuits through encoding the signed numbers to 2's complement, which is also a standard technique used in chip design, and provides significant improvements by

Belief Propagation Decoder for LDPC Codes Based on VLSI Implementation
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ABSTRACT: Low density parity check (LDPC) codes are most widely used error correcting codes (ECC). Because of their popularity they are used in several applications such as the digital satellite broadcasting system (DVB-S2), Wireless Local Area Network (IEEE 802.11

Basic Introduction to VLSI Technology with Processing Steps for Bipolar Junction Transistors: A Review
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ABSTRACT In present electronics era, VLSI technology become is one of the most important and demandable theme. Behind this many reasons are presents include device portability, device size, large amount of features, cost, reliability, speed and many more. VLSI

AN AUTONOMOUS INTELLIGENT ROBOT VISION COMPUTATIONAL SENSORS IN VLSI
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ABSTRACT Traditional approaches for solving real-world problems using computer vision have depended heavily on CCD cameras and workstations. As the computation power of workstations doubles every 1.5 years, they are now better able to handle the large amount

Fully Reused VLSI Architecture of FM0/Manchester Encoding Technique for Memory Application
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Abstract: In this paper a fully reused VLSI architecture of FM0/Manchester encoding technique for memory application has been proposed. In this paper we are encoding the 1 bit data into 16 bit data and storing it into a memory of certain address location given by

An Efficient VLSI Architecture for FIR Filter Using Multi-Bit Flip-Flops
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Abstract Recent advances in mobile computing and multimedia applications demand high- performance and low power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-impulse Response (FIR) filtering. In the existing

DSRC Applications in Intelligent Transportation System using SOLS Technique for fully reusedVLSI Architecture
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Abstract:The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dc-balance, enhancing the signal reliability.

VLSI Implementation of Reversible Watermarking Algorithm
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Abstract:This paper presents VLSI design approach and implementation of Lifting based Reversible Watermarking Algorithm. 5 by 3 Lifting based Discrete Wavelet Transform based image watermarking algorithm is proposed. It is attractive algorithm because of easier

Variable Body Biasing (VBB) Based VLSI Design Approach to Reduce Static Power
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Abstract:In CMOS integrated circuit design there is a swap among static power consumption and technology scaling. Recently, the power density has improved due to combination of higher clock speeds, greater functional integration, and smaller process

DESIGN OF MEMORY EFFICIENT VLSI ARCHITECTURE FOR REAL TIME MULTIMEDIA APPLICATION
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Abstract:On-chip memory hierarchy for a video contains the data memory and the context memory organizations for better optimization. Compressing the memory space is important aspect in VLSI, in order to reduce the power consumption, power dissipation and area.

Role of Low Power VLSI in Electronic and Digital Image Processing Practical Techniques Applications
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ABSTRACT In digital images when we used computer algorithms to perform image processing this term is generally called digital image processing. In the past, VLSI designers were mainly focused in area, performance, reliability and cost. But in today's world of

Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design: A Review
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Abstract Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under

A Feasible Approach to Design a Cmos Domino Circuit at Low Power VLSI Application Design
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Abstract: Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge

Single-ElectronTransistor Logic for High Reliability of Moore's Law and Low Power VLSI
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Abstract: The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors that are embedded per square inch on integrated circuits had doubled every 18 months since the integrated circuit was invented. But as per latest trends in VLSI

Multiobjective VLSI Circuit Partitioning Using ACO for Optimal Solution
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Abstract:The acceleration of the product to market cycle of VLSI based technology products dictates continuously refining design and implementation methodologies. Circuit partitioning is a physical design methodology which divides a given circuit into segments abiding by

VLSI System Design Using High Level Synthesis Tools
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Page 1. Lab Experiment: VLSI System Design Using High Level Synthesis Tools By:

FPGA Design of Reconfigurable Binary Processor Using VLSI
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Abstract:Binary image processing is a powerful tool in many image and video applications. In this paper we proposed efficient hardware architecture of Binary image processor for low power applications and also propose an Efficient Majority Logic Fault Detection algorithm

Dual AGC Model Implementation of the Inner Hair Cell and Auditory Nerve IC in NeuromorphicVLSI
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ABSTRACT-An analog inner hair cell and auditory nerve has been implemented for the persons with hearing disabilities. The designed circuit uses fully balanced circuits to reduce the mismatch of the signals that enters through the hearing aid. Ultra low power

Analog VLSI Implementation of Neural Network Architecture
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Abstract: Artificial intelligence is realized using artificial neurons. In the proposed design, we are using Artificial neural network to demonstrate the way in which the biological system processes in analog domain. The analog components like Gilbert Cell Multiplier (GCM),

Design of High Speed VLSI Architecture for 1-D Discrete Wavelet Transform
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Abstract: The work presents an implementation of discrete wavelet transform (DWT) using systolic array architecture in VLSI. The architecture consists of filter unit, storage unit and control unit. This performs calculations of low pass and high pass coefficients by using

VLSI IMPLEMENTATION OF IEEE754-2008 STANDARD FOR FINANCIAL TRANSACTIONS
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ABSTRACT Financial transactions are specified in decimal arithmetic. Until the introduction of IEEE 754-2008, specialized software hardware routines were used to perform these transactions but it incurred a penalty on performance. There is a need for accurate

Carbon Nanotube Prospects as On Chip VLSI Interconnects
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Abstract:within the confines of the topic we aim to acquaint the need, present trend and viability of the research in CNT as on-chip VLSI interconnects. The need to discuss the topic arises from the fact that the conventional materials used as interconnects like Cu/Al are

Efficient and high speed vlsi modelling of fm0/manchester encoding using sols technique and clock gating technique for dedicated short range communication
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Abstract-To promote intelligent and smart transportation services into our daily life the dedicated short range communication is an advanced technique. Data encoding techniques like FM0 and Manchester encoders are used to promote communication among vehicles.

A Low-Power VLSI Technique for Portable Electronic Devices
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Abstract: In portable electronic devices that operate on battery power, it is essential to have power saving techniques to increase the operating time as they are energy constrained. This paper presents a novel power saving technique supported by two design models for

VLSI IMPLEMENTATION OF LOW-POWER ADAPTIVE FIR FILTER USING DISTRIBUTED ARITHMETIC
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Abstract:The main objective is to design DA based adaptive filter in order to decreasing the logic complexity. Throughput is increasedby using parallel Look Up Table (LUT) update and concurrent implementation of filtering and weight-update operations. DA uses

VLSI HARDWARE MODELING OF DYNAMIC RNS STRUCTURE FOR HIGHEND COMPUTATIONS
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ABSTRACT This paper presents a dynamic structure for binary-to-residue number system (RNS) conversion modulo {2n±k} using macro structures. This structure is based only on adders and constant multipliers. This concise work is motivated by the existing {2n±k}

VLSI IMPLEMENTATION OF 2-D FDWT IMAGE SCALING PROCESSOR
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ABSTRACT: The block diagram of the proposed scaling algorithm. It consists of a sharpening spatial filter, a clamp filter, and a bilinear interpolation. The sharpening spatial and clamp filters serve as pre filters to reduce blurring and aliasing artifacts produced by

VLSI IMPLEMENTATION OF HIGH PERFORMANCE DISTRIBUTED ARITHMETIC (DA) BASED ADAPTIVE FILTER WITH FAST CONVERGENCE FACTOR
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Abstract: The key objective of this paper is to provide an idea for VLSI Implementation of RLS algorithm for noise cancellation with real time analog inputs. In this paper, we present an efficient architecture for the implementation of distributed arithmetic based multiplier

VLSI Based Adaptive Modulation and Adaptive OFDM
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Abstract:-In this paper, adaptive modulation technique is presented for Orthogonal Frequency Division Multiplexing (OFDM) based wireless communication system. The design of adaptive modulation is done through Very Large Scale Integration (VLSI) System

Space Compaction and Use of Minimal Logic Gate in VLSI Test Circuit Design by Uniquely Developed Algorithm Based on Graph Theoretical Approach
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Abstract:The design and implementation of space-efficient hardware for built-in self-testing circuit is very important step for synthesizing very large scale integration circuits. This research presents a new technique for merging output test vectors. The proposed

Graphene Based Planar VLSI Interconnects
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Abstract-Recently graphene nano-ribbon is a strong candidate for future VLSI interconnects systems. Cu interconnect systems were used in past but as technology node decreases the above interconnect system faced many problems. The VLSI interconnects which are

Efficient Carry Select Adder Using VLSI Techniques With Advantages of Area, Delay And Power
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Abstract: Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power

VLSI Based 16 Bit ALU with Interfacing Circuit
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ABSTRACT: The ALU is one of the most important module in a CPU and it can be modified during most instruction executions. So more bit of operation of the ALU is important task. In this project 16 bit ALU is designed using VHDL and it is interfaced with RAM and ROM.

Review Paper on High Speed VLSI Architecture for AES Algorithm
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Abstract:Now a day's large number of internet and wireless communication users has led to an increasing demand of security measures and devices for protecting the user data transmitted over the unsecured network so that unauthorized persons cannot access it. As

A NOVEL DESIGN APPROACH TO INCREASE THE SPEED OF VLSI CIRCUITS IN MIXED-SIGNAL ENVIRONMENT
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ABSTRACT Currently the mixed signal circuits like A/D and D/A converters are being designed either by MATLAB, C C++ or VHDL-AMS. But, these languages do not give detailed information at the architecture level. Though VHDL-AMS (VHSIC Hardware

A Radix Based Parallel VLSI Architecture for Finding the First W Max/Mini Values
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Abstract: VLSI architectures for finding the first W (W 2) maximum (or minimum) values are required in the implementation of several applications such as non-binary LDPC decoders, K-best MIMO detectors and turbo product codes. In this work a parallel radixsort-based

High-Speed VLSI Circuit Simulator
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Abstract With the rapid increase in the processing speed and scaling in electronic feature sizes of integrated circuits below 45nm, the analysis and simulation of high speed interconnects has become a critical prerequisite for electrical engineers. Unlike in the past

Modified SA Algorithm for Wirelength Minimization in VLSI Circuits
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Abstract:In modern VLSI circuits, number of parameters viz, placement of components, dead space (un occupied space in the layout), wire length has to be minimized. The defined problems are non deterministic and NP hard optimization problem. Hence probabilistic (

VLSI Designing of High Speed Parallel Multiplier–Accumulator Based On Radix4 Booths Multiplier
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ABSTRACT In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of ripple carry adder (RCA), the performance was improved. Since

IMAGE PROCESSING IN SECURE MANNER USING VLSI
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Abstract-Advanced Encryption Standard (AES) have been widely used in data encryption and decryption. The application of steganography in encrypted data is reported in a recent article. Any type of data can be practically hidden inside any image, without detectably

VLSI Implementation of Area Efficient Fast Parallel Fir Digital Filters Based On Fast Fir Algorithm
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Abstract: This paper proposes new parallel fir structures to reduce the hardware complexity of higher order Finite Impulse Response (FIR) filter with symmetric coefficients based on Fast FIR Algorithms (FFAs). The objective is to design an area-efficient Fast Parallel Finite-

VLSI POWER IN A NUTSHELL
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Electronic has been emerging its counterpart ever since the semiconductor was born. Now it has been developed throughout few decades and changed world into upside down. Electronic has evolved from vacuumed tubes to highly complex electronics designs

VLSI Implementation of Vedic Multiplier Using Urdhva–Tiryakbhyam Sutra in VHDL Environment: A Novelty
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Abstract: This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware

Analog VLSI Implementation of Feed Forward Neural Network for Signal Processing
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Abstract: With the emergence of VLSI Technology in electronic industry, the numerous applications of integrated circuits in high-performance computing, consumer electronics, and telecommunications has been rising steadily, and at a very fast pace. Artificial intelligence

VLSI IMPLEMENTATION OF ALU USING QUATERNARY SIGNED DIGIT FOR SIGNED AND UNSIGNED NUMBERS
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Abstract: In this paper, we proposed a new number system for ALU. In binary number system carry is a major problem in arithmetical operation. We have to suffer O (n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry

VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System
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Abstract-With the binary number system, the speed of arithmetic operations are limited by formation and propagation of the carry. Using quaternary signed digit (QSD) number system both carry free addition and borrow free subtraction can be achieved. The QSD number

A Comparative Study of Various VLSI Architecture for Discrete Wavelet Transform
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Abstract:The wavelet transform has itself as a useful tool in the field of 1-dimensional and 2- dimensional signal compression systems. Due to the growing importance of this technique, there is an increasing need in many working groups for having a development

IMPLEMENTATION OF FM0 AND MANCHESTER ENCODING FOR DSRC APPLICATIONS IN VLSI
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Abstract:The dedicated short-range communication is a one-or two-way medium range communication that can be divided into two categories: automobile-toautomobile and automobile-to-roadside. The safety issue consists of blind-spot, forewarning about

The authors validate the need for employing the self-timing principle for matching of modules in VLSI circuitry. Formal models of specification and analysis of
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The current intensive development of microelectronic computer circuitry opens up prospects for creating systems on the basis of very large-scale integrated (VLSI) circuit-. redictions indicate that, by the end of the 198Ofs, manufacture of VLSI

A Novel Vlsi DHT Algorithm For A Highly Modular And Parallel Architecture
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Abstract: In the current scenario so many advanced techniques are finding a way as a substitute for complex DFT. One of such type of technique is Discrete Hartley Transform. The requirement of only real arithmetic computations for the proposed technique makes it

To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques
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Abstract:-Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate

An Efficient Design of Optimized Low Power Dual Mode Logic Circuits Using VLSI Technology
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Abstract-This project represents a dual mode logic circuit for low power applications. Now a day's power consumption is the major role in chip design. If the area ofthe chip is reduced, the power consumption and the delays are increased due tosome effects like, cross talk,

Design of Novel Domino Circuits For High Performance And Energy Efficient VLSI Design
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ABSTRACT: In this work, a new domino circuit is proposed, which has a lower leakage and higher noise immunity without dramatic speed degradation for wide fan-in gates. The technique which is utilized in this work is based on comparison of mirrored current of the

Optimization of power and area using majority voter based fault tolerant VLSI circuits
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Abstract:This paper proposes a new voter circuit for tolerating stuck-at-faults in digital circuits. We consider in this paper single stuck-at type faults, occurring at a gate input. A stuck-at-fault may adversely affect on the functionality of the user implemented design. A

Comparative Analysis of CMOS Low Noise Amplifiers in 45 nm VLSI technology
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Abstract-The paper represents simulation and design of Low Noise Amplifier in a 45nm CMOS technology at 77 GHz frequency. Here we have proposed a comparative analysis of single ended and current reuse LNA. The LNA function is used to amplify signals without

VLSI Circuits and Systems Letter
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Abstract This letter presents a novel improved delay estimation methodology during scheduling in high level synthesis (HLS) for application specific computing. In general during delay estimation from scheduling during HLS, only functional unit delay is

VLSI IMPLEMENTATION OF ENCODING TECHNIQUEFOR EFFICIENT HARDWARE UTILIZATION IN DSRCAPPLICATIONS
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Abstract:The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dc balance, enhancing the signal

AVOID SYNCHRONIZATION LATENCY USING VLSI IMPLEMENTATION
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ABSTRACT The phenomenon of metastability is inherent in clocked digital logic. Many techniques have been presented for minimizing metastability, both for crossing clock domains, and for handling asynchronous inputs. Flip-flops are among these systems and

Overview of Testing Power Switches in VLSI Circuits
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Abstract:This paper presents a comparative discover of power switches. Power switches are increasingly becoming dominant leakage power reduction technique. Hence, fast and efficient DFT resolution for examination and diagnosis of power switches is far demanded

VLSI Design of Data Processing Architecture for Wireless Sensor Nodes
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Abstract:Sensor network processors introduce an unprecedented level of compact and portable computing. Sensor processors have a wide variety of applications in medical monitoring, environmental sensing, industrial inspection, and military surveillance.

Low Power VLSI Implementation of Adaptive Noise Canceller Based on Least Mean Square Algorithm
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Abstract: This paper presents VLSI implementation of adaptive noise canceller based on least mean square algorithm. First, the adaptive parameters are obtained by simulating noise canceller on MATLAB. Simulink model of adaptive noise canceller was developed

Sub word Partitioning and Signal Value based Clock gating Scheme for Low Power VLSIApplications
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Abstract The low power optimization techniques are very crucial for next generation wireless communication and battery powered signal processing applications. Several low power optimization techniques at circuit level and device level were implemented in past two

Realization of VLSI Architecture of Defuzzifier Unit
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Abstract-Fuzzy system used in control system, data mining, expert system. The fuzzy logic control system consist of a fuzzifier, fuzzy rule base, inference engine and defuzzifier. fuzzification and defuzzification are the two important process in the fuzzy logic control

VLSI Architecture of Centre of Gravity Based Defuzzifier Unit
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Abstract:In fuzzy control systems, fuzzification and defuzzification are two important procedures. Defuzzification is an important part in the implementation of a fuzzy system. The fuzzy data obtained from the fuzzification process is not suitable for real time applications,

Review on Low Power Design Using Comparator for VLSI Design Circuit
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ABSTRACT: The zone of low power and rapid planning of simple to-advanced converters (Adcs) has been a testing issue in the course of the most recent decade. The rate improvement of serial connections and the rising correspondence advances has slanted

A NEW VLSI ARCHITECTURE FOR 32/33/47/48 MULTIBAND FLEXIBLE DIVIDER USING 2/34/5 PRESCALER
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Abstract:This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulseswallow topology and the designed is modeled using Verilog simulated using Modelsim and

Efficient VLSI Implementation Based On Constructive Neural Network Algorithms
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Abstract: C-Mantec is a new neural network algorithm that adds competition between neurons with thermal perceptron learning rule. The neuron learning is ruled by the thermal perceptron rule that guarantees the stability of the learnt information while the architecture

VLSI Design of Power Efficient Reversible LFSR Using Pseudo Reed-Muller Expressions
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Abstract:Power dissipation is considered as one of the most important factors while designing a circuit. Reversible logic has become a promising technology in low power design. It is because reversible logic utilizes only very less power, thereby leading to less

TECHNIQUE FOR DETECTING MEMORY ERRORS IN JPEG 2000 USING VLSI TECHNOLOGY
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Abstract: This paper presents novel techniques to mitigate the effects of SRAM memory failures caused by low voltage operation in JPEG2000 implementations. We investigate error control coding schemes; specifically single error correction double error detection

DESIGN AND IMPLEMENTATION OF INTEGER DCT ARCHITECTURES FOR HEVC IN VLSITECHNOLOGY
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ABSTRACT: High Efficiency Video Coding (HEVC) inverse transform for residual coding uses 2-D 4x4 to 32x32 transforms with higher precision as compared to H. 264/AVC's 4x4 and 8x8 transforms resulting in an increased hardware complexity. In this paper, an

VLSI Implementation of Double-Base Scalar Multiplication on a Twisted Edwards Curve with an Efficiently Computable Endomorphism
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Abstract. The verification of an ECDSA signature requires a doublebase scalar multiplication, an operation of the form Q where G is a generator of a large elliptic curve group of prime order n, Q is an arbitrary element of said group, and k, l are two





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