ENGINEERING RESEARCH PAPERS

verilog research papers 2015 IEEE PAPER




DESIGN AND IMPLEMENTATION OF I2C SINGLE MASTER ON FPGA USINGVERILOG
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Abstract: This paper focuses on the design of I2C single master which consists of a bidirectional data line ie serial data line (sda) and serial clock line (scl). This protocol has the ability to support multiple masters. I2C is a two-wire, bidirectional serial bus that provides

Extending gNOSIS for System Verilog HDL Static Analysis
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Abstract Software engineering tools for Hardware Design Languages (HDL) lag behind traditional software development tools by decades. However as heterogeneous computing becomes more pervasive, productive programming in HDLs will become vital. To this end,

ASIC Design and Implementation of UART with DFT logic for Built-in Self-test usingVerilog HDL
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ABSTRACT Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver/Transmitter abbreviated UART, mostly used for short distance, low speed, low cost data exchange between processor and peripherals. UART allows full

A Verilog Compiler Proposal for VerCPU Simulator
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Abstract:Verilog is a widely used Hardware Description Language (HDL) for VLSI design and modeling. As a language developed with hardware execution concurrency in mind, Verilog can be mapped onto a dedicated processor for higher simulation throughput. The

Synthesis Simulation Model of Parallel Lift Controller Using Verilog
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Abstract-Machines are made to reduce human efforts and to save one's time. The machines are elegantly built to suit the formal surroundings. Thus machines were made according to the human need. The high growth of the semiconductor industry over the past two

Implementation and Performance Analysis of RSA Algorithm Using Verilog
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ABSTRACT This paper proposes an efficient method to implement RSA decryption algorithm. RSA cryptosystem is the most attractive and popular security technique for many applications, such as electronic commerce and secure internet access. There are few end-

Design of a Modified Gabor Filter with Vedic Multipliers Using Verilog HDL
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Abstract:Gabor Filters are widely used in all kinds of image processing. Gabor Filters include a memory, a controller and an arithmetic logic unit. The Gabor Filter designed in this project has a RAM type Memory, but a few changes were made in the Controller and the

AN EFFICIENT IMPLEMENTATION OF DA-BASED RECONFIGURABLE FIR DIGITAL FILTER USING VERILOG HDL
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Abstract: In this paper, we present the design optimization of one-and two-dimensional fullypipelined computing structures for area-delay-powerefficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-

Adaptive Techniques in Verilog Implementation of Area-Delay Efficient using QCA Binary Adders
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Abstract: As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach

Design of Multisized Output Cache Controller using Verilog
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Abstract: This paper describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequence the read and write of the cache storage array. Most of modern

ETHERNET IP CORE VERIFICATION USING SYSTEM VERILOG HDL
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Abstract:Functional verification of IP is an essential process in the chip/System on Chip (SoC) design process, since this would ensure correct functionality of the IP with the SoC. This paper intends to highlight the functional verification process of an Ethernet IP core,

High Speed and Power Optimized Parallel Prefix Modulo Adders using Verilog
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Abstract: The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder.

Implementation of Adaptive Viterbi Decoder using Verilog HDL
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Abstract: Forward Error Correction techniques are utilized for correction of errors at the receiver end. Convolutional encoding is an FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian

REALIZATION OF PULSE SHAPING FIR INTERPOLATION FILTER USING VERILOG
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ABSTRACT: Here This Optimization technique for designing are configurable VLSI architecture of an interpolation filter for multi-standard digital up converter, To reduce the power and area consumption. Most of the area is occupied in the design of FIR filter the

Design and Hardware Implementation for RC4 Stream Cipher by using Verilog HDL
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Abstract: Cryptography is the only practical method for protecting information transmitted through communication networks. The hardware implementation of cryptographic algorithms plays an important role because of growing requirements of high speed and high level of

Design and Implementation of Serial Peripheral Interface Protocol Using Verilog HDL
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Abstract-The objective of this paper is the design and implementation of SPI (serial peripheral interface) master and slave using verilog HDL. The SPI (serial peripheral interface) is a type of serial communication protocol that transfers synchronous serial data

Design and Synthesis of 32* 32 Bit Multi-precision Reconfigurable Multiplier by usingVerilog HDL
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Abstract: In this paper, we present a multi-precision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance

Design and Implementation of 3D-DWT in Verilog HDL using Lifting Scheme
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Abstract: The wavelet transform is a more effective tool than the Fourier and Short Time Fourier transform. Wavelet transform provides a multi resolution representation. This paper proposes an improved version of lifting based 3-D Discrete Wavelet Transform (3DDWT)

Implementation of I 2 C Protocol by using Verilog HDL
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Abstract: The I2C bus is a popular serial, two-wire interface used in many systems because of its low overhead. The two-wire interface minimizes interconnections so ICs have fewer pins, and the number of traces required on printed circuit boards is reduced. Capable of



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