verilog IEEE PAPER 2016
A comprehensive Verilog-A VCSEL model for 20Gb/s optical interconnect transceiver circuit design
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Abstract: Directly-modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in short-reach optical interconnect applications. In order to enable efficient optical interconnect transceiver systems operating at data rates in excess of 20Gb/s, cosimulation
A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment
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This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to
A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment
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Abstract. This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a
High Speed IEEE-754 Quadruple Precision Floating Point Multiplier Using Verilog
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Abstract Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Quadruple, double, and single precision floating point multipliers are
Implementation of Dynamic RAMs with clock gating circuits using Verilog HDL
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Abstract--Modern world's major concern is to minimize power consumption by the best way possible. Usage of clock gating technique to minimize dynamic power in sequential circuit is one of the best methods. This paper concentrates on the methods how to restrict the
Implementation and Analysis of Different Line Coding Schemes using Verilog
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Abstract:Line Coding is a discipline in the field of telecommunication which governs several kinds of sophisticated coding methods for transmitting a digital signal. It is intensively employed in baseband communication systems. In educational institutions, Line Coding is
IEEE 1149.1 Test Acess Port (JTAG) Verification using verilog simulation
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Abstract:-The major causes of board manufacturing defects are: missing components, wrong components, mis-oriented components, broken track (opens), shorted tracks (track-to-track shorts), pin-to-pin solder opens, pin-to-pin solder shorts. To consider the shorts, we
Generation Of PWM Using Verilog In FPGA
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Pulse width modulation (PWM) signals which are to be used in various power electronics application like power converters and inverters is presented. Pulse Width Modulation (PWM) triggers the gate terminals of the power electronic semiconductor devices like thyristors,
A Simple C to Verilog Compilation Procedure for Hardware/Software Verification
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ABSTRACT The objective of this work is two-fold:(1) to build a simple trusted translator from C programs to a hardware description language (in this case Verilog) and (2) to illustrate its application to the formal verification of hardware and software systems using highly
Realisation of 4 To 16 Reversible Decoder Using Verilog
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Abstract: Reversible logic has become an emerging field for research. The main advantage of reversible logic is power reduction and this advantage have drawn up a significant interest in this field. The aim of the paper is to realize the decoder using Fredkin gate
Electronic Model of Human Brain using Verilog
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Abstract:Computers are man-made machines which work according to the given set of inputs and perform some operation on the input to generate a new set of outputs. They can be programmed to perform huge and complex task yet they lack imagination and ability to
Realization of Multiplier Design with Novel Adaptive Hold Logic Using Verilog HDL
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Abstract:Digital multipliers are the most critical arithmetic functional units. The overall performance of the systems depends on the throughput of the multiplier. At the same time, the negative bias temperature instability effect occurs when a transistor is under negative
Language Wars in the 21st Century: Verilog versus VHDL–Revisited
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ABSTRACT Back in the late 20th century, the VHDL versus Verilog debate was compared to a religious war that neither side could win. At various times, knowledgeable industry leaders have predicted that each HDL would prevail, but it seems we still live in a bilingual world.
Design and Verification of AMBA AHB-Lite protocol using Verilog HDL
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Abstract:The SOC plan confronts a crevice between generation limit and time to market weights. The outline space develops with changes underway limits as far as measure of time to plan a framework utilizing these abilities. On one hand, shorter product life cycles are
RISC (16-bits) Processor Design Using VerilogFPGA
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Abstract:The reduced instruction set computer, or RISC, is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. The most common RISC microprocessors are ARM, DEC Alpha
Realization of Aging-Aware Reliable Multiplier Using Verilog
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Abstract: Digital multipliers are among the most vital arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Transistor aging results in circuit delay degradation over time, and is a growing concern for future systems.
DESIGN OF 8 PORT ROUTER FOR NOC USING VERILOG
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ABSTRACT Multiprocessor system on chip is emerging as a new trend for System on chip design but the wire and power design constraints are forcing adoption of new design methodologies. Researchers pursued a scalable solution to this problem ie Network on
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