ENGINEERING RESEARCH PAPERS

vlsi IEEE PAPER 2016




A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications
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Abstract. This paper proposes the implementation of a low power and high speed Vedic Divider based on ancient Indian Vedic mathematics. In this paper, an algorithm based on the ParavartyaYojayet is applied, throughout this sutra the propagation delay and power

VLSI Implementation of High Speed MAC Unit Using Karatsuba Multiplication Technique
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Abstract–This research work is devoted to design speed optimized Multiply Accumulate Unit. MAC Unit is a digital coprocessor that plays a prominent role in digital domain to perform various sophisticated tasks such as FFT, DFT, resolving various complex equations being

Convex Optimization approach to VLSI Floorplan Design
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Abstract The floor planning problem aims to arrange a set of modules on a chip area so as to optimize an appropriate measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. Fixed-outline floor planning is

A Simple VLSI Spherical Particle-Induced Yield Predictor
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ABSTRACT A simple VLSI particle-induced yield predictor has been developed that allows us to predict the entire yield of VLSI and also to analyze the bottleneck processing steps and faults. Particles with spherical shape are generated in the production equipment for each

Special Section on VLSI Design and CAD Algorithms
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The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences announces a forthcoming Special Section on VLSI Design and CAD Algorithms to be published in December 2016. The objective of the special section is to discuss new

VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA CLAA
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In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA

Performance Evaluation of Different Multipliers in VLSI using VHDL
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Abstract: Multiplier modules are common to many DSP applications. The fastest types of multipliers are parallel multipliers. Among these, the Array multiplier is the basic one. However, they suffer from more propagation delay. Hence, where regularity, high

A Survey of Various Metaheuristic Algorithms Used to Solve VLSI Floorplanning Problem
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Abstract-Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-hard problem. Modern Abstract This chapter presents an introduction to the microfluidics field and microfluidic biochips. We discuss the main fluid propulsion principles used by modern microfluidic platforms, with a focus on continuous flow microfluidic biochips, which is the topic of this

Economic Full Adder Circuit in VLSI Using Shannon Expansion
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Abstract This paper presents an efficient high-speed 8-bit full adder using Shannon's expansion. The adder is designed and implemented using 180nm CMOS process technology. The proposed adder provides a good compromise between cost and

Voltage-Island based Floorplanning in VLSI for Area Minimization using Meta-heuristic Optimization Algorithm
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Abstract Floor planning is the primary step of the physical design in the Very Large Scale Integration (VLSI) design flow. It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections. In the modern physical design

Comparison of Temperature Dependent Performance and Analysis of SWCNT bundle and Copper as VLSI Interconnects
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Abstract This paper presents the analysis and the performance of Single Walled Carbon Nanotube (SWCNT) bundle as VLSI interconnects by considering the effect of temperature for different technology nodes. An equivalent temperature dependent RLC circuit model

Novel Automatic Test Pattern Generator (ATPG) for degenerated SCAN-BIST VLSI Circuits
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Abstract-This paper attempts to show the innovative Test Pattern Generator (TPG) using linear assembly of bit generator. Test power reduction done by the active usage of under adaptive exchanging of clock is used. New test pattern generator is designed to generate

VLSI Implementation of Discrete Linear Convolution using Vedic Mathematics (Real and Complex Numbers)
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Abstract This paper focuses on implementing Linear convolution algorithm using Vedic Mathematics to achieve higher speed and low power. Vedic Mathematics is an ancient Indian System for performing calculation. The Vedic multiplier is designed by using the

ANFIS AND BPNN BASED POWER ESTIMATION METHOD FOR CMOS VLSI CIRCUITS
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Newer advancement in VLSI technology has led to integration of large number of transistors in a single chip and complexity of the circuits increases rapidly so that the power estimation became vital task at this stage. This work presents an Adaptive Neuro Fuzzy Inference

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm
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Abstract. Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication

Area Efficient and High Speed VLSI Based Pipelined 64-Point Radix-4 Mixed Architecture Design
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Abstract In this paper, a new VLSI based Radix-4 FFT architecture is developed by combining the mixed radix and pipelining architectures. Proposed architecture named as Radix-4 Combined Single Path Delay Feedback (SDF)-Multipath Delay Commutator (

Ultra Low Power VLSI Design: A Review
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ABSTRACT Leakage power plays a vital role in current CMOS technologies. As feature size shrinks leakage power also increasing. Power dissipation becomes as important consideration as performance and area for chip design in present days VLSI industry.

VL7201 CAD FOR VLSI CIRCUITS UNIT I VLSI DESIGN METHODOLOGIES
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UNIT I VLSI DESIGN METHODOLOGIES Introduction to VLSI Design methodologies Review of Data structures and algorithms Review of VLSI Design automation tools Algorithmic Graph Theory and Computational Complexity Tractable and Intractable problems general

Literature Review on High Frequency Affects and Methodologies in Reduction of EM Interference and IR Drop in VLSI Circuits
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Abstract: This paper presents the literature review on electromagnetic interference, and power leakage minimization. To reduces the EM interference and IR drop by using various methodologies applied by researchers. For any research work or in an effort to introduce

VLSI Implementation of Text to Image Encryption Algorithm based on Private Key Encryption
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Abstract:In cryptographic applications, the data sent to a remote host are encrypted at the source machine using an encryption key and then the encrypted data are sent to the destination machine, where it is decrypted to get the original data. Thus the attacker will

VLSI IMPLEMENTATION OF HIGH SPEED AREA EFFICIENT ARITHMETIC UNIT USING VEDIC MATHEMATICS
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Abstract: High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multifunctions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and

VLSI Implementation of ADC Using Aliasing Free Pulse Width Modulation
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Abstract:The Analog to Digital Converters (ADCs) have been in existence for more than 30 years and an integral part of Software Defined Radio, sensor applications and other potential applications. This paper discusses about the implementation of ADC using the

A New Parallel VLSI Architecture in Real Time by using Microcontroller
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Abstract: In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Abstract:Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

Widths of Channel Routing in VLSI Design
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Abstract:In VLSI design, one of the most important detailed routings is the channel routing. Given a channel with length n in 2-layer Manhattan model, Szeszler proved that the width

VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers
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Abstract: In many digital systems, the most important and basic component ismultiplier and adder which are recommended for implementing the concepts of DSP systems, arithmetic and logic functions and multimedia applications. In many real time digital applications,

A VLSI Implementation of a Proposed Modified Controller Area Network (CAN) Protocol for Car Automation
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ABSTRACT The design, simulation and implementation of a CAN protocol controller for the Car automation. A multimaster serial communication protocol. The CAN Controller designed will function as the interface between the anti-lock brake and other nodes of car

Review of Fully Reused VLSI Architecture of Channel Encoding Using SOLS Technique for DSRC Applications
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Abstract: Dedicated short-range communications are one-way or two-way short-range to medium-range wireles s communication channels specifically designed to push the intelligent transportation system into our daily life. So I am processing the fully reused

Design and VLSI Implementation of NXN Binary Multiplier Using Successive Approximation of (N-1) X (N-1) Binary Multipliers
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Abstract: In VLSI technology, power consumption and delay becomes a major problem in multipliers. To reduce these issues we propose a new multiplier algorithm that combines numerical transformation and shift and add technique. In this design NXN bitmultiplication

Performance and Reliability Analysis for VLSI Circuits Using 45nm Technology
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Abstract:Performance and reliability analysis tests the VLSI circuits over a prolonged period of time at different conditions. Therefore, performance and reliability of an inverter circuit and two CMOS gate interconnect circuit, a combination of two inverters connected

AN APPROACH TO PERFORMANCE CHARACTERISTICS OF SWCNT VLSI INTERCONNECTS SPECIFIC TO 22NM TECHNOLOGY NODE
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ABSTRACT Single wall carbon nanotubes (SWCNTs) holds extremely good electrical and mechanical properties in conjugation to their application in sub nanometer regime and a viable replacement to Cu interconnects. This indeed raises a need to realize their

Fully Reconfigured VLSI architecture of FM0, Manchester and Miller Encoder for DSRC Applications
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Abstract-Intelligent transportation system (ITS) aim to provide innovative services at different modes of transport and traffic management. Dedicated short range communication (DSRC) is a new technique to promote the intelligent transportation into our daily life. DSRC

Optimised Hybrid VLSI Architecture Using Hadamard Transform
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Abstract:Fully-pipelined and parallel modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N= 4. It

One Day Symposium On Current Trends in Embedded Systems and VLSI Technology
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The main goal of symposium was to bridge the gap between industry and academic arena. To achieve the same, an expert lecture series containing five sessions from various industry experts covering five different domains of Embedded Systems and VLSI Technology were

VLSI Circuits and Systems Letter
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Abstract–In this letter, a synchronous current mode logic Serializer and Deserializer (SerDes) is presented. The proposed technique consumes less power and faster than self- timed CMOS SerDes and wave pipelined asynchronous SerDes. This technique has the

Implementation of VLSI Based Robust Router Architecture
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Abstract: In this paper, we introduce networking solution by using VLSI architecture techniques to router design for networking system to provide control over the network. We attempts to overcome latency and time reduction issue and can provide multipurpose

A Review on Clock Gating Methodologies for power minimization in VLSI circuits
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Abstract This research paper gives the introduction of the various clock gating techniques. It also provides the basic clock gating principles, benefits, limitations and enhancements in traditional clock gating scheme. Also it provides the details of parameters which can affect

VLSI IMPLEMENTATION OF KNOWLEDGE-BASED NEURAL NETWORK BACK PROPAGATION
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ABSTRACT Neural Networks have a wide range of applications in analog and digital signal processing. Nonlinear activation function is one of the main building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most used nonlinear activation

SIMULATED ANNEALING ALGORITHM FOR MODERN VLSI FLOORPLANNING PROBLEM
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Abstract In floorplanning, our aim is to determine the relative locations of the blocks in the chip and the objective is to minimize the floorplan area, wirelength. Generally, there are so many strategies in VLSI floorplanning like area optimization, wirelength optimization,

A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs
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Abstract:Modern logic and physical synthesis tools provide numerous options and parameters that can drastically impact design quality; however the large number of options leads to a complex design space difficult for human circuit designers to navigate. We

VLSI IMPLEMENTATION OF CORDIC BASED ROBOT NAVIGATION PROCESSOR
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ABSTRACT This paper proposes the design of multiplier-less processor through CORDIC algorithm and radio frequency identification (RFID) technology for implementing the VLSI architecture. The robot navigation ameans the ability of the robot to establish its own

VLSI Implementation of Boolean Algebra based Cryptographic Algorithm
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Abstract:FPGA is an integrated circuit, which can be reconfigured by designers themselves. FPGA are reprogrammable silicon chips. Field Programmable Gate Arrays (FPGA) are used for hardware implementations of cryptographic algorithm. This paper

AN EFFICIENT VLSI BASED ERROR IDENTIFICATION AND CORRECTION OF TEXT DATA SEQUENCE TRANSMISSION
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ABSTRACT The Bloom filter technique is used to create hash function transform in a given test data sets. It is a spaceefficient probabilistic data structure. This proposed technique is used for many applications where the amount of source data would require an large hash

Fully Reused VLSI Architecture of Miller Encoding using SOLS Technique for DSRC Applications
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Abstract:Dedicated Short Range Communication is a simplex or duplex short range to medium range wireless communication. It is used to support Intelligent Transport System (ITS) applications such as electronic toll collection, parking lot, border crossing

Low Power VLSI design Methodologies Power Management
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Abstract:Low power is the major challenge for todays electronics industries. Power dissipation is an important consideration in terms of performance and space for VLSI Chip design. Power management techniques are generally use to designing low power circuits

Comparative Analysis of VLSI circuits using multigate devices.
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Abstract-The enhancement in the scaling technology has increased the need of low power based circuits. In nanometer regime, CMOS based circuit may not be used due to problem in its fundamental material, short channel effect and high leakage. There is need of better

Review Paper on VLSI Architecture for Carry Select Adder
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Abstract: A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers

CMOS VLSI Design Lab 4: Full Chip Assembly
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In this final lab, you will assemble and simulate your entire MIPS microprocessor! You will build your top level chip cell by connecting the datapath, aludec, and controller_synth to a padframe cell containing the I/O pads. chip will have the same inputs, outputs, and

OPTIMAL UNATE DECOMPOSITION METHOD FOR SYNTHESIS OF MIXED CMOS VLSICIRCUITS
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ABSTRACT Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale

VLSI Based Robust Router Architecture
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Abstract: In this paper, we introduce networking solution by using VLSI architecture techniques to router design for networking system to provide control over the network. We attempts to overcome latency and time reduction issue and can provide multipurpose

VLSI IMPLEMENTATION OF 12-BIT SAR ADC OPTIMIZING DYNAMIC POWER
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ABSTRACT Autonomous acoustic-sensor nodes rely on low power circuit techniques to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of a low-power analog to digital converter (ADC). The

A Review on VLSI Floorplanning Optimization using Metaheuristic Algorithms
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Abstract:In the VLSI physical design, floorplanning is an essential design step, as it determines the size, shape, and locations of modules in a chip and as such it estimates the total chip area, the interconnects, and, delay. Computationally, VLSI floorplanning is an

Adiabatic Logic Circuits for Low Power VLSI Applications
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Abstract: The power dissipation has become a major design issue in VLSI circuits. As the system size is shrinking gradually it has become one of the prime concerns for the designers. The power dissipation can be reduced by introducing different design

VLSI IMPLEMENTATION OF AREA EFFICIENT RESIDUE ARCHITECTURE FOR CRYPTOGRAPHIC APPLICATIONS
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ABSTRACT: Cryptography is a science of utilizing mathematics to encrypt and decrypt data. Cryptography enables to store sensitive information or transmit it across insecure networks so that it cannot be read by anyone except the intended recipient. Area efficient residue

Reconfigurable VLSI architecture of FM0/Manchester Encoder for DSRC Applications
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ABSTRACT Intelligent transportation systems aim to provide innovative services at different modes of transport and traffic management generally use FM0 and Manchester codes for encoding. These codes enhance the signal reliability with dc balance. The coding

Review paper on VLSI Design of modulo 2 n 1 Adder using Residue Number System
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Abstract:Modular adder is one of the key components for the application of residue number system (RNS). Moduli set with the form of 2n+ 1 can offer excellent balance among the RNS channels for multi-channels RNS processing. As one of the processor's ALU performance

VLSI DESIGN OF A NOVEL PRESTO WITH PROGRAMMABLE PRPG
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Abstract: This paper describes a low-power (LP) programmable generator capable of reducing pseudorandom take a look at patterns with desired toggling levels and increased fault coverage gradient compared with the best-to-date intrinsical self-test (BIST)-primarily