ENGINEERING RESEARCH PAPERS

VLSI-Very Large Scale Integration-2017 IEEE PAPER




Design and Implementation of Enhanced Leakage Power Reduction Technique in CMOS VLSI Circuits
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Abstract The rapid increase of semiconductor technology and growing demand for portable devices powered up through battery has led the constructors to scale down the feature size; resultant reduced threshold voltage as well as thereby enabling integration of incredibly

VLSI Implementation of 8051 MCU with Decoupling Capacitor for IC-EMC
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Abstract In recent years, several new methods for IC-level electromagnetic compatibility (EMC) testing have been introduced. Therefore, a handy vehicle for IC-EMC testing is required to validate the effectiveness of the new IC-EMC testing methods. This paper Gain-Cell eDRAM (GC-eDRAM) is an interesting, high-density alternative to SRAM and conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications, including ultra-low power systems such as biomedical implants [17], wireless

Delay Optimized Full Adder Design for High Speed VLSI Applications
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Abstract-The most widely used arithmetic operation in digital applications is addition. Full adder is the most important building block in digital signal processors and controllers as it is used in arithmetic logic circuit (ALU), in the floating point unit and in case of cache or

VLSI Design of Reconfigurable Filter for Multi-Standard SDR Application
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Abstract: The design of future multi-standard systems is very challenging. Flexible architectures exploiting processing commonalities of the different set of standards cohabiting in the device offer promising solutions. This paper presents a graphical approach for the

targeting area optimization in reconfigurable device (FPGA) using VLSI Technique
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Abstract Forward error correction (FEC) plays an important role in the field of telecommunication and information theory as it improves the capacity of a channel. It has been observed that Reed Solomon Error Corrector is a powerful method for error detection

VLSI IMPLEMENTATION OF HIGH SPEED OPTIMIZED IMAGE SEGMENTATION USING PARALLEL PREFIX ADDER
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ABSTRACT Genetic algorithms (GA) come under a category of evolutionary algorithms where the elements of search space are binary strings or arrays of other elementary types. The roots of GAs go back to 1950s where they are applied to computer aided simulations to

High-Level Synthesis Based VLSI Architectures for Video Coding
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High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard. Emerging applications like free-viewpoint video, 360degree video, augmented reality, 3D movies etc. require standardized extensions of HEVC. The standardized extensions of HEVC include

MAX Tree Extraction Enabled Area and Energy Efficient Median Filter Design: A VLSI Design Approach
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Abstract The exponential rise in the demands of a cost effective, power and area efficient de- noising filter design for varied image processing and allied application, in this paper a novel MAX-Tree Extraction (MTE) algorithm enriched median filter has been proposed. To achieve

VLSI Architecture of Encoding using Sols Technique for Reducing Power in DSRC
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ABSTRACT Now a days DSRC plays a vital role. It is one way or two way short range to medium range communication. Such as safety applications, commercial vehicle applications, emergency warning systems for vehicle. DSRC adopts codes such as

A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI Architecture
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Abstract-Convolutional encoding and viterbi algorithm are basic concepts of error correction method. Viterbi algorithm is one of decoding method for data error correction. In VLSI area, the design challenges are usually about its power, area consumption, speed, complexity,

Review Paper On Implementation Of Low Power Hard Decision Viterbi Decoder In VLSI
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Abstract-For correction of errors at the receiver end, convolutional encoding is used which is a forward error correction technique. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraints length. This paper proposed

AN EFFICIENT VLSI ARCHITECTURE FOR AES AND its FPGA IMPLEMENTATION
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Abstract-Security is the most vital element in information communication system, where greater randomization in secret keys increases the safety as well as the complexity of the cryptography algorithms. The algorithms corresponding to DES, Triple DES are

AN EFFICIENT VLSI ARCHITECTURE FOR 64-BIT VEDIC MULTIPLIER
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ABSTRACT Multipliers are very significant part of any processor or computing device and DSP processor. Reversible logic circuits have many applications in quantum computing, nanotechnology and low power CMOS technology, optical information processing. A

VLSI Architecture for High Performance Montgomery Modular Multiplication
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Abstract: Montgomery Modular Multiplication is a method for performing fast modular multiplication. Montgomery Modular Multiplication is used for encryption process in Public Key Cryptography. This paper proposes a Semi Carry Save (SCS) based Montgomery

CORDIC-BASED VLSI ARCHITECTURE FOR FLAT TOP WINDOWING IN REAL TIME SPECTRAL ANALYSIS
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Abstract:one of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify

Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits
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Abstract: Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault

15A04604 VLSI DESIGN (CBCC-II)
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_____________________________________________________R15 Page 56 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR B. Tech IV-I Sem.(EIE) LTPC 3 1 0 3 15A04604 VLSI DESIGN (CBCC-II) Course Objectives: To understand VLSI circuit design

VLSI DESIGN OF POWER EFFICIENT 4-BIT SIGNED ADDER FOR ARITHMETIC APPLICATIONS
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ABSTRACT Area efficient ultra low power CMOS digital integrated circuits are one of the emerging technologies for the modern portable systems. Requirement of fewer transistors on chip and less power consumption for the operation of these devices proves the efficiency

INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES RESEARCH TECHNOLOGY VEDIC MATHEMATICS FOR VLSI DESIGN: A REVIEW
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ABSTRACT Multiplication and division are the most critical arithmetic operation carried out in any digital logic algorithm such as digital signal processing, in cryptography for encryption and decryption algorithm, ALU design and in other logic computation. Thrust in higher

VLSI IMPLEMENTATION OF MULTIPLIER BASED BLOCK LMS ADAPTIVE FILTER
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Abstract:An analysis is made on the computational complexity of Block Least Mean Square Adaptive Filter where the filter computation is decomposed into M sub filters and M= N/L where N is the filter size, L is the block size. The decomposition is done inorder to favour

VLSI IMPLEMENTATION OF HIGH SPEED VITERBI DECODER
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Abstract: Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The

Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design
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Abstract:-As the in semiconductor industries progress by following Moore's law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in

Efficient Architecture for Error Control Coding Using VLSI Implementation
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Abstract-Viterbi algorithm is widely used as a decoding technique for convolutional codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power. This

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power
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Abstract:The rise in technology has demanded the use of more and more components on chip. This rise has led to rise in power dissipation and a major challenge for circuit designers. Due to scaling, the reduction of threshold voltage in CMOS circuits increases the

An Efficient VLSI Implementation of OFDM based on Multiplier Less FFT IFFT
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Abstract: Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier system where data bits are encoded to multiple subcarriers, while being sent simultaneously. OFDM is implemented by using the combination of FFT and IFFT. The Eight point DIT-FFT DIF

VLSI Implementation Of Encryption Algorithm Based On Regions
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Abstract-This work proposes a novel scheme for encryption algorithm based data security hiding. In the first work, a content owner encrypts the original uncompressed text using an encryption key. Then, it may compress the least significant bits of the encrypted text using a

VLSI Implementation of Eye Detection System
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Abstract:The eye detection is one of the most challenging problems in many applications such as image processing, pattern recognition and computer vision. This paper introduces efficient vlsi implementation of eye detection system. Face detection is a very important part

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Abstract:Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

Low Power Consumption Using CMOS VLSI Design in Modern Trends
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The revolution of wireless communication, portable and mobile devices has consistently demanding the designer to design the device for low power consumption. Power loss becomes a main parameter of integrated circuits, particularly for portable computers and

Area and Delay Optimized Arithmetic Architectures of VLSI for ACT Design
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Abstract: The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly- exact computation of DCT require floating point arithmetic, are multiplier intensive, and

IMPROVED AND PERSUASIVE ADDER FOR ADVANCED VLSI APPLICATIONS
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ABSTRACT In hardware planning, adder is a computerized part which performs expansion of numbers. To figure quick number juggling operations, carry select adder (CSLA) is one of the promising adders utilized as a part of lashings information handling support of lessening

VLSI ARCHITECTURES FOR 2-DDiscrete WAVELET TRANSFORM USING KS ADDER
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Abstract:Discrete wavelet transform (DWT) is a mathematical technique that provides a new method for signal processing. It decomposes a signal in the time domain by using dilated/contracted and translated versions of a single basis function. The 2-D DWT is highly

FAST VLSI ARCHITECTURE FOR REDUNDANT BASIS MULTIPLIERS
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Abstract: Redundant Basis Multiplier Over Galois Field (GF (2m)) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper, we have proposed a novel recursive

IMAGE AND VLSI TECHNIQUES DEVELOPMENT OF EARLY DETECTION OF BREAST CANCER AND DIAGNOSE USING MAMMOGRAMS
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ABSTRACT In this paper we proposed a method to detect the breast cancer accurately in the early stage using image processing and VLSI techniques. In the existing methods cancer affected regions of the mammogram were detected but could not calculate the affected

Reduction of Power Consumption in VLSI by Energy Efficient Low Power CMOS Design
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Abstract: In today's electronic industry low power has emerged as a principal theme. Energy efficiency is one of the most critical features of modern electronic systems designed for high speed and portable applications. Reduction of power consumption makes a device more

Course Structure and Syllabus For M. Tech.(VLSI and Embedded System) Two Year (Four Semester) Course (wef July 2017)
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I. To serve the society and nation, by providing high quality engineering educational programs to the students, engaging in research and innovations that will enhance the skill and knowledge and assisting the economic development of the region, state, and nation

VLSI DESIGN FOR HUMAN HEALTH MONITERING AND MEDICAL ALERT SYSTEM BASED ON FPGA, MEMS AND SPECIAL SENSOR NETWORK
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Abstract: The main objective of this paper is used to monitor the physical health conditions of elderly people, patients. Where the system detects and informs the abnormal health condition (eg blood pressure, pulse rate and fall detection) by using the smart sensor

Design and Analysis of Various Standard Multipliers Using Low Power Very Large Scale Integration (VLSI)
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Abstract-This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using Verilog HDL. Multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and

An efficient VLSI architecture for Iterative Logarithmic Multiplier
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Abstract:Logarithmic Number System (LNS) based multiplier plays a significant role in the fields of Digital Signal Processing (DSP), Image processing and Neural network which needs a lot of arithmetic operation. In all arithmetic operations, the multiplication is most

Review Paper on Efficient VLSI Architecture for Carry Select Adder
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ABSTRACT A adder is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design many types of

VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR WIRELESS SENSOR NETWORK
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ABSTRACT: In this paper we studied the implementation of Manchester coding is being described. Manchestercoding technique is a digital coding technique in which all the bits of the binary data are arranged in a particular sequence. These sections operate completely

AN EFFICIENT VLSI ARCHITECTURE FOR THE MODIFIED CONVOLUTIVE BLIND SOURCE SEPARATION
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ABSTRACT This will presents an efficient Very Large Scale Integration (VLSI) design for Convolutive Blind Source Separation (CBSS). Information maximization (Infomax) approach is adopted for CBSS network. CBSS chip design mainly includes Infomax filtering modules

INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES RESEARCH TECHNOLOGY FULLY REUSED VLSI ARCHITECTURE OF DSRC ENCODERS
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ABSTRACT Dedicated short-range communications (DSRC) are one-way or two-way from short-range to medium-range wireless communication channels specifically designed to push the intelligent transportation system into our daily life. The DSRC standard generally

Analysis and Comparison of Methods to Reduce Leakage Power and Latency to Improve Performance of VLSI Circuits
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Abstract: Power dissipation in one of the major concerns of VLSI circuit designers with the launch of battery held devices and applications, power consumption in the circuit also increased exponentially. Leakage current became an overriding factor in nanometer CMOS

VLSI ARCHITECTURE FOR EXPLOITING CARRY-SAVE ARITHMETIC USING VERILOG HDL
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Abstract:-The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carrysave arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic Abstract A low power and efficient 2-D Discrete Wavelet Transform architecture is proposed. Previous DWT architectures utilized flipping structures or modified lifting based schemes. In this over-lapped strip based scanning is utilized to reduce the number of clock cycles for

VLSI Implementation of Lifting Based 3-D DWT
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Abstract-This paper proposes an efficient architecture for lifting based 3-D DWT Lifting based for video/image signal using parallel pipeline technique. The main objective of this paper is to minimize the critical path delay in computing the 9/7 lossy lifting steps with

Vlsi Implementation Of Flexible Architecture For Decision Tree Classification In Data Mining
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Abstract. The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the

VLSI ARCHITECTURE FOR EXPLOITING CARRY-SAVE ARITHMETIC USING VERILOG HDL
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Abstract: The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmeticdominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic

A spike based learning neuron in analog VLSI
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H Philipp, M Mahowald, L Watts heim.ifi.uio.no Abstract Many popular learning rules are formulated in terms of continuous, analog inputs and outputs. Biological systems, however, use action potentials, which are digital-amplitude events that encode analog information in the inter-event interval. Action-potential

HIGH SPEED AREA EFFICIENT VLSI ARCHITECTURE FOR DCT AND DHT ALGORITHM
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Abstract:Low-power layout is one of the most vital challenges to maximize battery life in portable devices and to save the energy during simulation operation. Image and video compressor is widely used in Discrete Cosine Transform (DCT). Many types of techniques

INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES RESEARCH TECHNOLOGY REVIEW PAPER ON EFFICIENT VLSI AND FAST FOURIER
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ABSTRACT A fast Fourier transform (FFT) is any fast algorithm for computing the DFT. The development of FFT algorithms had a tremendous impact on computational aspects of signal processing and applied science. The decimation-intime (DIT) fast Fourier transform (FFT)

VLSI Architecture of Configurable Low Complexity Hard Decision Viterbi Decoder
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ABSTRACT A Viterbi algorithm has served as a powerful method for decoding of the convolutional code so as to control errors in data transmission over a noisy channel. It is based on maximum likelihood algorithm for decoding the data. However, the hardware

Improved Power Gating Techniques for Reduction of Noise and Leakage Power in VLSI Circuits
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ABSTRACT Design of complex arithmetic logic circuits considering ground noise, leakage current, active power and area is a challenging task in VLSI circuits. In this paper, a comparative analysis of high performance power gating schemes is done which minimizes

METHOD OF EFFICIENT VLSI ARCHITECTURE FOR DECIMATION-IN-TIME FAST FOURIER TRANSFORM OF REAL-VALUED DATA
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ABSTRACT: The decimation-in-time (DIT) fast Fourier transform (FFT) very often has advantage over the decimation-in-frequency (DIF) FFT for most real-valued applications, like speech/image/video processing, biomedical signal processing, and time-series analysis,

A Review on various DSRC application of FM0/Manchester encoder-decoder based on VLSI
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Abstract: The process of communication mainly depends on encoding and decoding of data transmission. The secure transmission of data is very important in communication system. For the secured data transmission there are different types of techniques are used for

Design of Efficient High Secure Image Encoding using VLSI
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ABSTRACT: The community of the research in the last few years has received significant attention from the field of approximate computing, particularly in different signal processing context. The compression algorithms of the image and video such as MPEG and JPEG and

VLSI DESIGN OF A NOVEL LP-LFSR BASED PROGRAMMABLE PRPG ARCHITECTURE
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Abstract: This paper describes a low-power (LP) programmable generator capable of reducing pseudorandom take a look at patterns with desired toggling levels and increased fault coverage gradient compared with the best-to-date intrinsically self-test (BIST)-primarily

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