2-stage pipeline ADC
A 12b 50MS/s 3.5 mW SAR assisted 2-stage pipeline ADC
FREE-DOWNLOAD [PDF] CC Lee… – VLSI Circuits (VLSIC), 2010 research
A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b
SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the
large 6b stage resolution. A “half-gain” MDAC reduces the output swing and increases