ASIC and FPGA implementations of H. 264 DCT and quantization blocks



FREE-DOWNLOADRC Kordasiewicz Image Processing, 2005. ICIP , 2005
In the search for ever better and faster video compression standards H.264 was created. With
it arose the need for hardware acceleration of its very computationally intensive parts. To address
this need, this paper proposes two sets of architectures for the integer discrete transform





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