Implementation of algorithms to determine the capacitance sensitivity of interconnect parasitics in the Magic VLSI layout tool
FREE-DOWNLOAD [PDF] NKH Huang – 2009
Capacitance Sensitivity of Interconnect Parasitics in the Magic VLSI Layout Tool by Nick
Kuan-Hsiang Huang A new set of capacitance models is imple- mented in the Magic VLSI layout
tool to improve the capacitance accuracy based on 2.5D capacitance models.