Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
FREE-DOWNLOAD G Keramidas, P Xekalakis… – Transactions on High-Performance …, 2009 The equipment used for this work is a donation by Intel Corporation under Intel Research Equipment Grant #15842. Page 18. Recruiting Decay for Dynamic Power Reduction 21 References In: Proc. of the Int. Conference on VLSI Design
Low Power Delay Optimised Buffer Design using 70nm CMOS Technology
FREE-DOWNLOAD D Sharma… – International Journal of Computer …, 2011 slight increase in threshold voltage causes a large amount of leakage power reduction with only dissipation has been achieved while maintaining same delay as compared to the existing design. can be used to provide power efficient solutions for portable VLSI applications at
Low-Power CMOS VLSI Design lecture notes
FREE-DOWNLOAD LD Van – 2010 – Lan-Da Van VLSI-DSP-14-9 Low Power System Design Space Power budgeting, S/H partitioning, power management, core selection System Algorithm Architecture Logic/Circuit Process Algorithmic reduction, data transformation, CSE, low-complexity operation