Using Hard Macros to Reduce FPGA Compilation Time
FREE-DOWNLOAD C Lavin, M Padilla, S Ghosh, B Nelson… – … Conference on Field …, 2010 – The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized,
RAMP Gold: An FPGA-based architecture simulator for multiprocessors
FREE-DOWNLOAD Z Tan, A Waterman, R Avizienis, Y Lee… – Proceedings of the …, 2010 – We present RAMP Gold, an economical FPGA-based archi- tecture simulator that allows rapid early design-space explo- ration of manycore systems. The RAMP Gold prototype is a high-throughput, cycle-accurate full-system simulator that runs on a single Xilinx
FPGA design and implementation of a real-time stereo vision system
FREE-DOWNLOAD S Jin, J Cho, X Dai Pham, KM Lee… – … and Systems for …, 2010 Stereo vision is well-know ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction […]