digital signal processing-33


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SHEAR PERFORMANCE OF PREFABRICATED JAPANESE MUD WALL UNITS–SUPERFICIAL FISSURE GROWTH EVALUATION USING DSP
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BI Hassel, A Kitamori, K Jung ,bath.ac.uk
Abstract: Shear tests on small prefabricated mud wall units (PMWU) were carried out. The
units consist of a bamboo grid plastered with a mixture of clay, sand and thatch fibres inside
a timber frame. Unlike the conventional Japanese mud wall, the PMWU can be produced 

DSP BASED POWER ANALYZING SYSTEM FOR ONSITE MEASUREMENTS
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WMS Wijesinghe ,imeko.org
Abstract- A three-phase power analyzing system based on digital signal processing (DSP)
has been developed as a traveling standard for onsite power calibration. The design and
operation is described for a sampling wattmeter capable of measuring power parameters 

Design of video processing and testing system based on DSP and FPGA
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LJ Xu Honga, C Xi’aia, G Xuexiaa ,Proc. of SPIE Vol ,144
ABSTRACT Based on high speed Digital Signal Processor (DSP) and Field Programmable
Gate Array (FPGA), a video capture, processing and display system is presented, which is of
miniaturization and low power. In this system, a triple buffering scheme was used for the 

Errors in floating-point DSP calculations
FREE DOWNLOAD [PDF] from bme.hu
V Pálfi ,mit.bme.hu
Abstract-Quantization errors like ADC errors and roundoff errors are similar in the sense that
they are difficult to analyze and predict, and therefore need careful tests/measurements. This
paper discusses roundoff errors: analyzes the needs and summarizes the possibilities. It 

Compiling for a Heterogeneous Vector Image Processor In Proceedings, Ninth Workshop on Optimizations for DSP and Embedded Systems (ODES-9)
FREE DOWNLOAD [PDF] from ensmp.fr
F Coelho ,ssh.cri.ensmp.fr
Abstract We present a new compilation strategy, implemented at a small cost, to optimize
image applications developed on top of a high level image processing library for an
heterogeneous processor with a vector image processing accelerator. The library 

Real-Time DSP-Based License Plate Character Segmentation Algorithm Using 2D Haar Wavelet Transform
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Z Jeffrey, S Ramalingam ,Advances in Wavelet , 2012 ,cdn.intechopen.com
The potential applications of Wavelet Transform (WT) are limitless including image
processing, audio compression and communication systems. In image processing, WT is
used in applications such as image compression, denoising, speckle removal, feature 

ePUMA: Embedded Parallel DSP Processor Architecture with Unique Memory Access
FREE DOWNLOAD [PDF] from polimi.it
J Wang, J Sohl, O Kraigher, L Dong ,conferenze.dei.polimi.it
To meet the continuously increasing computational load acquired from various signal
processing applications, the DSP processor design has gone through a development
process that involves explorations of different types or levels of parallelism. For example, 

DSP: Robust Semi-Supervised Dimensionality Reduction using Dual Subspace Projections
FREE DOWNLOAD [PDF] from wku.edu
S Yan,  2010 IEEE/WIC/ACM International , 2010 ,acadmedia.wku.edu
Abstract—High-dimensional data usually incur learning deficiencies and computational
difficulties. We present a novel semi-supervised dimensionality reduction technique that
embeds high-dimensional data in an optimal lowdimensional subspace, which is learned 

Robust and Energy-Efficient DSP Systems via Output Probability Processing
FREE DOWNLOAD [PDF] from uiuc.edu
R Abdallah ,Proc. of Int. Conf. on Computer Design, 2010 ,vlsi.csl.uiuc.edu
Abstract—This paper proposes to employ error statistics of nanoscale circuit fabrics to
design robust energy-efficient digital signal processing (DSP) systems. Architectural level
error statistics are exploited to generate probability or the reliability of each output bit of a 

Advanced Design of DSP-based High Precision Event Timer
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V Vedin ,Electronics and Electrical Engineering, 2009 ,ee.ktu.lt
A good many various techniques associated with time measurements have been developed
over years. In most of applications it is time intervals that have to be measured. Traditionally
they are measured by employing time interval measurement techniques. However, during 

Expression Rematerialization for VLIW DSP Processors with Distributed Register Files
FREE DOWNLOAD [PDF] from nthu.edu.tw
CJ Wu, CH Lu ,International workshop on compilers , 2009 ,pllab.cs.nthu.edu.tw
Abstract. Spill code is the overhead of memory load/store behavior if the available registers
are not sufficient to map live ranges during the process of register allocation. Previously,
works have been proposed to reduce spill code for the unified register file. For reducing 

Neonatal DSP-4 treatment impairs 5-HT1B receptor reactivity in adult rats. Behavioral and biochemical studies
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M Ferdyn-Drosik, P Nowak, K Bojanek ,Pharmacological , 2010 ,if-pan.krakow.pl
Abstract: To examine the effect of a central noradrenergic lesion on the reactivity of the 5-
HT1B receptor we compared intact male rats with rats in which noradrenergic nerve
terminals were largely destroyed with the neurotoxin DSP-4 (50 mg/kg× 2, on the 1st and 

Design and Implementation of Sensorless Control for Four-Switch, Three-Phase Brushless DC Motor Drive based on DSP Technology
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AH Niasar, A Vahedi ,Iranian Journal of Electrical and , 2009 ,sid.ir
Abstract—Brushless DC (BLDC) motor is attracting much interest due to its high efficiency,
good performance and ease of control for many applications. Moreover, reducing of the
drive components is more attractive for low cost applications. This paper presents the


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