dual sampling SAR ADC
An energy-efficient dual sampling SAR ADC with reduced capacitive DAC
FREE-DOWNLOAD [PDF] B Kim, L Yan, J Yoo, N Cho… – Circuits and Systems, …, 2009
Abstract— This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling
step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically
at both input sides of comparator, the MSB cycling step can be hidden by hold mode.