FULL ADDER-VLSI PROJECT
Design of a novel fault tolerant reversible full adder for nanotechnology based systems
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Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. A reversible circuit maps each input
Low-Power and High-Performance 1-Bit CMOS Full – Adder Cell.
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In this paper a new low power and high performance adder cell using a new design style called Bridge is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption
Optimal design of a reversible full adder
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Four designs for reversible full – adder circuits are presented. The implementation of these logic circuits into electronic circuitry is based on c-MOS technology and pass-transistor design. In particular, we investigate the use of the fundamental building block of Fredkin. We
An efficient quantum-dot cellular automata full – adder
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The most important mathematical operation is addition. Other operations such as subtraction, multiplication and division are usually implemented by adders. An efficient adder can be of great assistance in designing arithmetic circuits. QCA is a promising
A high speed 8 transistor full adder design using novel 3 transistor XOR gates
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The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been
A novel low power and high performance 14 transistor CMOS full adder cell. J
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Full adders are important components in applications such as Digital Signal Processors (DSP) architectures and microprocessors. Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power
Power and delay comparison in between different types of full adder circuits
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This paper describes the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a better metric to evaluate circuit performance is power
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
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This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called XOR (3T) is
New design methodologies for high-speed mixed-mode CMOS full adder circuits
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This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also
Low power CNTFET-based ternary full adder cell for nanoelectronics
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In a VLSI circuit, about 70 percent of area occupies by Interconnection. Such a large number of area occupation leads to many limitations of fabricating and applying in binary circuit implementation. Multiple-valued logic is one of the most proper way to improve the ability of
High speed gate level synchronous full adder designs
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Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND
Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18 µm CMOS Technology
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In this paper, The low power and high performance 1-bit full adder cell is proposed. The Gate Diffusion Input (GDI) technique has been used for the simultaneous generation of XOR and XNOR functions. Fourteen states of the arts 1-bit full adders and one proposed full
A robust asynchronous early output full adder
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A robust asynchronous full adder design corresponding to early output logic, synthesized using the elements of a standard cell library is presented in this paper. As the name suggests, the adder ensures gate orphan freedom and neatly fits into the self-timed system
High speed NP-CMOS and multi-output dynamic full adder cells
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In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using
Comparative analysis of different types of full adder circuits
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The Full Adder circuit is an important component in application such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. This paper discusses the evolution of full adder circuits in terms of lesser power
Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology.
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In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuits outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the
Low Power Full adder with reduced transistor count
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Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic gate. This paper proposes a new 3T-XOR gate with significant area and power savings. In most of the digital systems adder lies in the critical path that increases the overall
On the design of high-performance CMOS 1-bit full adder circuits
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In this paper, two high performance full adder circuits are proposed. We simulated these two full adder circuits using Cadence VIRTUOSO environment in 0.18 µm UMC CMOS technology and compared the Power dissipation, time delay, and power delay product
A novel full adder with high speed low area
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In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary
A six transistors full adder
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