free research papers-electronics and communication engineering-11
Jing Lin, Akshaya Srivasta, Andreas Gerstlauer, Brian L. Evans, Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems, Proceedings of the International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 2011. Ku He, Andreas Gerstlauer, Michael Orshansky, Controlled Timing-Error Acceptance for Low Energy IDCT Design, Proceedings of Design, Automation & Test in Europe (DATE), Grenoble, France, May 2011. Parisa Razaghi, Andreas Gerstlauer, Host-Compiled Multicore RTOS Simulator for Embedded Real-Time Software Development, Proceedings of Design, Automation & Test in Europe (DATE), Grenoble, France, May 2011. Rainer Dmer, Weiwei Chen, Xu Han, Andreas Gerstlauer, Multi-Core Parallel Simulation of System-Level Description Languages, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 2011. (invited paper) Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubhr, Jrgen Teich, A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2010. Andreas Gerstlauer, Host-Compiled Simulation of Multi-Core Platforms, Proceedings of the International Symposium on Rapid System Prototyping (RSP), Washington, DC, June 2010. (invited paper) Andreas Gerstlauer, Gunar Schirner, Platform Modeling for Exploration and Synthesis, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, Taiwan, January 2010. (invited paper) Gunar Schirner, Andreas Gerstlauer, Rainer Dmer, System-Level Development of Embedded Software, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, Taiwan, January 2010. (invited paper) Ardavan Pedram, David Craven, Andreas Gerstlauer, Modeling Cache Effects at the Transaction Level, Analysis, Architectures and Modeling of Embedded Systems, International Embedded Systems Symposium (IESS), Langenargen, Germany, edited by Achim Rettberg, Mauro Zanella, Michael Amann, Michael Keckeisen, Franz Rammig, Springer, ISBN 978-3-642-04283-6, September 2009. (best paper runner-up) Amal Banerjee, Andreas Gerstlauer, Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices, Analysis, Architectures and Modeling of Embedded Systems, International Embedded Systems Symposium (IESS), Langenargen, Germany, edited by Achim Rettberg, Mauro Zanella, Michael Amann, Michael Keckeisen, Franz Rammig, Springer, ISBN 978-3-642-04283-6, September 2009. Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara, Specify-Explore-Refine (SER): From Specification to Implementation, Proceedings of the Design Automation Conference (DAC), Anaheim, CA, July 2008. (invited paper) Gunar Schirner, Andreas Gerstlauer, Rainer Dmer, Automatic Generation of Hardware dependent Software for MPSoCs fromAbstract System Specifications, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, January 2008. Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dmer, Embedded Software Development in a System-Level Design Flow, Embedded System Design: Topics, Techniques and Trends, International Embedded Systems Symposium (IESS), Irvine, CA, edited by Achim Rettberg, Mauro Zanella, Rainer Dmer, Andreas Gerstlauer, Franz Rammig, Springer, ISBN 978-0-387-72257-3, June 2007. Dongwan Shin, Andreas Gerstlauer, Rainer Dmer, Daniel D. Gajski, An Interactive Design Environment for C-based High-Level Synthesis, Embedded System Design: Topics, Techniques and Trends, International Embedded Systems Symposium (IESS), Irvine, CA, edited by Achim Rettberg, Mauro Zanella, Rainer Dmer, Andreas Gerstlauer, Franz Rammig, Springer, ISBN 978-0-387-72257-3, June 2007. Gunar Schirner, Andreas Gerstlauer, Rainer Dmer, Abstract, Multifaceted Modeling of Embedded Processors for System Level Design, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 2007. Rainer Dmer, Andreas Gerstlauer, Dongwan Shin, Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components, Proceedings of the International SoC Design Conference, Seoul, Korea, October 2006. Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dmer, Daniel D. Gajski, Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Seoul, Korea, October 2006. Dongwan Shin, Andreas Gerstlauer, Rainer Dmer, Daniel D. Gajski, Automatic Generation of Communication Architectures, From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), Manaus, Brazil, edited by Achim Rettberg, Mauro C. Zanella, Franz Rammig, Springer, ISBN 0-387-27557-6, September 2005. Dongwan Shin, Andreas Gerstlauer, Rainer Dmer, Daniel D. Gajski, Automatic Network Generation for System-On-Chip Communication Design, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Jersey, NJ, September 2005. Andreas Gerstlauer, Dongwan Shin, Rainer Dmer, Daniel D. Gajski, System-Level Communication Modeling for Network-On-Chip Synthesis, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Shanghai, China, January 2005. Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, Multi-Metric and Multi-Entity Characterization of Applications for Early System Design Exploration, Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Shanghai, China, January 2005. Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, Retargetable Profiling for Rapid, Early System-Level Design Space Exploration, Proceedings of the Design Automation Conference (DAC), San Diego, CA, June 2004. Haobo Yu, Andreas Gerstlauer, Daniel Gajski, RTOS Scheduling in Transaction Level Models, Proceedings of the International Conference on Hardware/Software Codesign & System Synthesis (CODES+ISSS), Newport Beach, CA, October 2003. Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski, RTOS Modeling for System-Level Design, Proceedings of Design, Automation & Test in Europe (DATE), Munich, Germany, March 2003. Andreas Gerstlauer and Daniel D. Gajski, System-LevelAbstraction Semantics, Proceedings of International Symposium on System Synthesis (ISSS), Kyoto, Japan, October 2002. W. Mueller, R. Dmer, A. Gerstlauer The Formal Execution Semantics of SpecC, Proceedings of International Symposium on System Synthesis (ISSS), Kyoto, Japan, October 2002. Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer, Co-design of Emulators for Power electric Processes Using SpecC Methodology, Proceedings 28th Annual Conference of the research Industrial Electronics Society, Sevilla, Spain, November 2002. Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer, Co-design of Embedded Controllers for Power Electronics and Electric Systems, Proceedings International Symposium on Intelligent Control, Vancouver, Canada, October 2002. R. Dmer, A. Gerstlauer, D. Gajski, SpecC Methodology for High-Level Modeling, 9th research/DATC Electronic Design Processes Workshop, Monterey, April 2002. A. Gerstlauer, S. Zhao, D. Gajski, A. Horak, SpecC System-Level Design Methodology Applied to the Design of a GSM Vocoder, Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Kyoto, Japan, April 2000.
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