Area Efficient Full Subtractor Based on Static 125nm CMOS Technology IJTSRD


A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much more smaller.

G. Hemanth Kumar | K. Gopi | P. Gowtham | G. Naveen Balaji “Area Efficient Full Subtractor Based on Static 125nm CMOS Technology”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-6 , October 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd18860.pdf

Paper URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/18860/area-efficient-full-subtractor-based-on-static-125nm-cmos-technology/g-hemanth-kumar

call for paper Agricultural Engineering, international journal Chemical Engineering, ugc approved journals for engineering




Area Efficient Full Subtractor Based on Static 125nm CMOS Technology IJTSRD IEEE PAPER





2020 technology trends
2019-TOP-TECHNOLOGIES
2019 papers
2018-TOP-TECHNOLOGIES
2018 papers

IEEE PROJECTS 2019


IEEE PROJECTS CSE 2019
IEEE PROJECTS ECE 2019
IEEE PROJECTS EEE 2019
IEEE PROJECTS VLSI
IEEE PROJECTS EMBEDDED SYSTEM

IEEE PROJECTS


IEEE PROJECTS ECE
IEEE PROJECTS CSE COMPUTER SCIENCE
IEEE PROJECTS ELECTRICAL ENGINEERING
IEEE PROJECTS EEE

IEEE PROJECTS