Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology ijtsrd
In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.
by Tanusha Beni Vyas | Shubhash Chandra “Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology”
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019,
Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology ijtsrd IEEE PAPER
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