Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology ijtsrd



In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.

by Tanusha Beni Vyas | Shubhash Chandra “Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019,

URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdf

Paper URL: https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d–latch-using-32nm-cmos-technology/tanusha-beni-vyas

call for paper Distributed Computing, international journal Industrial Engineering, ugc approved journals Nuclear Engineering