High Performance Triplex Adder using CNTFET IJTSRD


Carbon Nanotubes Field Effect Transistors (CNTFETs) is used to implement a two new design of triplex half adder. conventional binary logic has a capable alternate called triplex logic, since it is possible to accomplish uncomplicatedness and energy efficiency in modern digital design due to shortened circuit overhead such as interconnect and chip area. Triplex decoders and binary logic gates are used to present two novel half adders. To obtain power, delay and power delay product the circuits are simulated using HSPICE . Recently reported designs are compared with these circuits. These triplex adders show delay and power advantage up to 40 and 39 % with less transistor count. So, using these half adders in complex arithmetic circuits will be advantageous.

by G. Naveen Balaji | S. Chenthur Pandian | D. Rajesh”High Performance Triplex Adder using CNTFET”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-5 , August 2017,

URL: http://www.ijtsrd.com/papers/ijtsrd2300.pdf

http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/2300/high-performance-triplex-adder-using-cntfet/g-naveen-balaji

call for paper Textile Engineering, international journal Software Engineering, ugc approved journals for engineering




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