Improving Analog Performance and Suppression of Subthreshold Swing using Hetero-Junction Less Double Gate Tunnel FETs IJTSRD


In this paper, we investigated a new device, Hetero-junction less (H-JL) Double Gate Tunnel Field Effect Transistors (DGTFET) with high-k. III-V semiconductor material (like InAs-Si) gives excellent performance when InAs uses at source side, because of low band gap of 0.36 eV it reduces the potential barrier height of source channel interface causing maximum carriers are fastly tunnel across the source to drain in ON state whereas Si, at the drain side as higher bandgap Of increasing the barrier height of drain channel interface causing lower quantum tunneling occur, as a result good ION/IOFF ratio. The InAs-source JLDGTFET with high-k (Hfo2) at 20 nm channel length provide a tremendous characteristics with high ratio , a point subthreshold swing (SS) and average SS is at room temperature. The simulation study of proposed device is done using sentaurus tools.

Dr. Prabha Shreeraj Nair”Improving Analog Performance and Suppression of Subthreshold Swing using Hetero-Junction Less Double Gate Tunnel FETs”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017,

URL: http://www.ijtsrd.com/papers/ijtsrd5780.pdf

http://www.ijtsrd.com/engineering/computer-engineering/5780/improving-analog-performance-and-suppression-of-subthreshold-swing-using-hetero-junction-less-double-gate-tunnel-fets/dr-prabha-shreeraj-nair

call for paper Water Resource Engineering, international journal Forestry Engineering, ugc approved journals for engineering




Improving Analog Performance and Suppression of Subthreshold Swing using Hetero-Junction Less Double Gate Tunnel FETs IJTSRD IEEE PAPER





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