Linear CMOS LNA IJTSRD


In this work, a highly linear Cascode CMOS LNA is presented. Linearity issues in RF receiver frontend are discussed, followed by an analysis of the specifications and requirements of a LNA through consideration of multi-standard LNA. Device non-linear characteristics cause linearity problems in the RF front-end system. To solve this problem, Post linearization technique for inductively degenerated L-deg common source Cascode Low Noise Amplifier is presented, which improves linearity performance with small gain loss and current consumption as consequence.The LNA presented has 1.0GHz – 3.2GHz frequency range designed using TSMC 0.18µm CMOS process. The linearized LNA achieves an IIP3 of 5.0 dBm, with P-1dB of -14 dBm, 13.8 dB gain max , NF 2.03dB and power utilization of 19.4 mWat 1.8 volt power supply

by Gaurav R. Agrawal | Leena A. Yelmule “Linear CMOS LNA”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-1 , December 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd19087.pdf

Paper URL:http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/19087/linear-cmos-lna/gaurav-r-agrawal

call for paper Electronics & Communication Engineering, international journal Electronics & Communication Engineering, ugc approved journals Electronics & Communication Engineering




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