Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment IJTSRD


Multipliers are the main key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors, ALU and etc.It improves the speed of the many processors. Vedic mathematics is mainly based on sixteen principles or word-formulae which are termed as Sutras .A high speed complex 16 *16 multiplier design by using urdhvatiryakbhyam sutra is used here, By using this sutra the partial products and sums are generated in one step which there by reduces the design of architecture in processors. It can be used in the applications such as convolution, Fast Fourier Transform (FFT) and in microprocessors. The propagation delay of the processors can be reduced by using this technology.

By N. Divya”Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-2 , February 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd7185.pdf

http://www.ijtsrd.com/engineering/electrical-engineering/7185/review-on-fpga-implementation-of-1616-vedic-multiplier-in-vhdl-environment/n-divya

call for paper Automotive Engineering, international journal Electrical Engineering, ugc approved journals for engineering




Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment IJTSRD IEEE PAPER





2020 technology trends
2019-TOP-TECHNOLOGIES
2019 papers
2018-TOP-TECHNOLOGIES
2018 papers

IEEE PROJECTS 2019


IEEE PROJECTS CSE 2019
IEEE PROJECTS ECE 2019
IEEE PROJECTS EEE 2019
IEEE PROJECTS VLSI
IEEE PROJECTS EMBEDDED SYSTEM

IEEE PROJECTS


IEEE PROJECTS ECE
IEEE PROJECTS CSE COMPUTER SCIENCE
IEEE PROJECTS ELECTRICAL ENGINEERING
IEEE PROJECTS EEE

IEEE PROJECTS