A Performance Degradation Tolerance Way Tagged Cache IJTSRD
For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high-speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults […]
A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction IJTSRD
Modern embedded processors includes both scratchpad memory (SPM) and cache memory in their architectures. SPM’s are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection(SEC-DED) and SEC-DED double-adjacent error correction(SEC-DED-DAEC) and parity duplication approach. […]
A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction IJTSRD
Modern embedded processors include both scratchpad memory (SPM) and cache memory in their architectures. SPM’s are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection (SEC-DED) and SEC-DED double-adjacent error correction (SEC-DED-DAEC) and parity […]
A Performance Degradation Tolerance Way Tagged Cache IJTSRD
For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high-speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults […]