A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction IJTSRD
Modern embedded processors includes both scratchpad memory (SPM) and cache memory in their architectures. SPM’s are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection(SEC-DED) and SEC-DED double-adjacent error correction(SEC-DED-DAEC) and parity duplication approach. […]
A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction IJTSRD
Modern embedded processors include both scratchpad memory (SPM) and cache memory in their architectures. SPM’s are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection (SEC-DED) and SEC-DED double-adjacent error correction (SEC-DED-DAEC) and parity […]