low power LDPC decode




Scalable and low power LDPC decoder design using high level algorithmic synthesis

FREE-DOWNLOAD [PDF] Y Sun, JR Cavallaro… – SOC Conference, 2009. SOCC …,
The VLSI layout view of this decoder with a core area of 1.2 mm2 (standard cells + SRAMs)
is shown in Fig.  R Memory (SRAM) P Memory (SRAM) Fig. 9. VLSI layout view of the LDPC
decoder TABLE II COMPARISON WITH EXISTING LDPC DECODERS 




IEEE PAPER UNITED STATES