on-chip interconnects


Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
FREE DOWNLOAD [PDF] 
AK Mishra, X Dong, G Sun, Y Xie… – Computer Architecture …, 2011
… Network-on-Chip (NoC) architectures: A packet-based NoC pro- vides a scalable interconnection
fabric for connecting the processor nodes, the on-chip shared cache banks and the on-chip
memory controllers [2]. On-chip routers and links constitute this scalable communication



COMMENT free research papers, vlsi





FREE IEEE PAPER





on-chip interconnects IEEE PAPER



2020 TECHNOLOGY