power consumption during test application



Reduction of power consumption during test application by test vector ordering [VLSI circuits]
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P Girard, C Landrault, S Pravossoudovitch… – Electronics …
… Circuit testing, VLSI The authors address the problem of testing VLSI circuits without exceeding
their power ratings during testing. The proposed approach is based on reordering test vectors
in a test sequence to minimise the switching activity of the circuit during test application.




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