processor IEEE PAPERS-2020



A central processing unit, also called a central processor or main processor, is the electronic circuitry within a computer that executes instructions that make up a computer program. The CPU performs basic arithmetic, logic, controlling, and input/output operations specified by the instructions in the program.

The ongoing megatrends in industry and academia like the Internet ofThings (IoT), the Industrial Internet of Things (IIoT) and Cyber-Physical Systems (CPS) present the developers of modern computer architectures with variouschallenges. A novel class of



Tube-based robust mpc processorin-the-loop validation for fixed-wing uavs
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Abstract Real systems, as Unmanned Aerial Vehicles (UAVs), are usually subject to environmental disturbances, which could compromise the mission accomplishment. For this reason, the main idea proposed in this research is the design of a robust controller, as

Compact domain-specific co- processor for accelerating module lattice-based key encapsulation mechanism.
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We present a domain-specific co- processor to speed up Saber, a post-quantum key encapsulation mechanism competing on the NIST Post-Quantum Cryptography standardization process. Contrary to most lattice-based schemes, Saber doesnt use NTT

Architecture of an mRNA processor
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The 3′-end processing of the three major classes of RNA polymerase II transcripts in metazoan cells polyadenylated messenger RNAs (mRNAs), histone mRNAs, and small nuclear RNAs (snRNAs) requires three distinct machineries that share common features In recent years, deep learning based diagnostic approaches have become more attractive. However, most of these methods are supervised diagnostic approaches. Developing a supervised diagnostic model requires a large number of labeled training data. And it is time

Analysis and elimination of noise-induced temperature error in processor thermal control
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Processor thermal control in real-time systems is crucial because overheated processors result in critical performance degradation or even system failure. The main challenges in processor thermal control in real-time systems are as follows:(i) the need to satisfy both Most modern parallel programs are written with the moldable property. However, most existing parallel computing systems treat such parallel programs as rigid jobs for scheduling, resulting in two drawbacks. The first is inflexibility and inefficiency in processor allocation

Analysis of dynamic laser injection and quiescent photon emissions on an embedded processor
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Security is increasingly widespread in many embedded devices. As technology scales, fault attacks are seen as becoming more relevant to many embedded devices, revealing secrets utilized within the silicon. Despite numerous publications in fault injection, laser fault

Binary quantum-inspired gravitational search algorithm-based multi-criteria scheduling for multi- processor computing systems
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A quantum-inspired hybrid scheduling technique is proposed for multi- processor computing systems. The proposed algorithm is a hybridization of principles of quantum mechanics (QM) and a nature-inspired intelligence, gravitational search algorithm (GSA). The principles ofThe interconnection of computers in networks, such as the Manufacturing Automation Protocols (MAP), brought the need to guarantee an optimum use of the resources involved. The optimization can be achieved by designing the network interface as a front-end Spiking neural networks (SNN) has been widely used to solve complex tasks such as pattern recognition, image classification and so on. The neuromorphic processors which use SNN to perform computation have been proved to be powerful and energy-efficient. These A many-core parallel approach of the multilevel fast multipole algorithm (MLFMA) based on the Athread parallel programming model is presented on the homegrown many-core SW26010 CPU of China. In the proposed many-core implementation of MLFMA, the data In the era of intelligence, the processing of a large amount of information and various intelligent applications need to rely on embedded devices. This trend has made machine learning algorithms play an increasingly important role. High-performance embedded

Processor
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Page 1. PREPROCESSOR BY PRITI JADHAV Page 2. Preprocessor Preprocessor processes source program before it is passed to compiler. IInpreprocessor COuOtoOmOpiler Produce a source code file with the preprocessing commands properly sorted out. Preprocessor Complier

Implementaion of RISC Processor on FPGA
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Abstract RISC (Reduced Instruction Set Computer) is a design methodology which supports small and simple set of instructions that all requires the same amount of time to get execute. The proposed processor been carried out with the Harvard Architecture which use separate In the current scenario the advent of automation technology is limited to industrial use only. This proposed system of Automatic food processor based on PLC and SCADA software is designed to cook food automatically as required by the user. This PLC based automated

The self modifying code (SMC)-aware processor (SAP): a security look on architectural impact and support
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Self modifying code (SMC) are code snippets that modify themselves at runtime. Malware use SMC to hide payloads and achieve persistence. Software-based SMC detection solutions impose performance penalties for real-time monitoring and do not benefit from This is a fairly detailed summary and extension of results from chapter 5 of [KMP14]. We go into considerable level of detail here, because i) the MIPS ISA is part of the formulation of every processor correctness theorem in this book and ii) all processor designs will be derived in one way or the

Robust Cache-Aware Quantum Processor Layout
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Quantum computation has taken over as one of the largest current research areas in computer architecture and information theory. With the potential to make a large number of factorization-based encryption methods obsolete, companies and governments around the

Realising a ProcessorNative Distributed Shared Memory Architecture
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The main research question is the effect of hardware memory By exploiting the UniMem memory scheme communication The applications memory demand has always challenged the In such a configuration, a centralised shared memory Any elements within a computing system

Macro ProcessorSystem Programming Operating System
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? It allows the programmer to write shorthand version of a program (module programming)? The macro processor replaces each macro instruction with the corresponding group of source language statements (expanding)? Normally, it performs no

Deep Learning Inference on the MPPA3 Manycore Processor
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We present the principles of deep learning inference on the MPPA Kalrays third- generation manycore processor . Unlike dedicated deep learning accelerators, the MPPA3 platform is also effective for image processing, signal processing, and numerical processing

ProcessorRetailer Markup and Pricing Decision: Insights from the US Beef Market 2011-16
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The real processorretailer markup for beef in the United States increases by 33% from to 201 a substantial and rare increase for a major agricultural commodity. Meanwhile, the processorretailer markup ratio increases from 40% to 50%. We explain the increase in

ON IMPLEMENTATION OF FFT PROCESSOR IN XILINX FPGA USING HIGH-LEVEL SYNTHESIS
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The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives theThe server models functioning in the industry are required to be more elastic in nature. They are constantly scaling-up and scaling-down on required computation power depending on different conditions. These elastic cloud platforms use accelerators like DSPs, TPUs, GPUs

Adaptive Speech Enhancement using DSP Processor
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Speech and text is the main medium for human communication. Digital signal processing plays a central role in the development of modern communication and information processing systems. In audio processing background noise is removed and required noise

CHALLENGES IN CHIP/ PROCESSOR LEVEL THERMAL ENGINEERING
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Central Processing Unit CPU popularly called Processor is termed the brain of the computer. This is where all processing of information takes place. Processor a very sensitive part and a determinant of what happens. This article runs a study on how a processor can Processing-intensive web server requests can lead to low Quality of Service (QoS), such as longer mean response time and lower throughput, which calls for a new web server software framework that can improve the performance of web servers. The characteristic of request

Stabilizing the virtual response time in single-server processor sharing queues with slowly time-varying arrival rates
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Motivated by the work of Whitt (Queueing Syst 81 (4): 341 37 2015) and Ma and Whitt (in: Winter simulation conference, pp 2598 260 2015), that studied performance stabilization in a\(GI_t/GI_t/1\) queue, this research study investigates the stabilization of the mean virtual

Hardware Acceleration for Elementary Functions and RISC-V Processor
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Page 1. Hardware Acceleration for Elementary Functions and RISC-V Processor Jing Chen Doctor of Philosophy School of Computer Science McGill University Montreal, Quebec 2020-05-15 A Thesis Submitted to the Faculty of Graduate Studies and Research in Partial Fulfillment of the Requirements

AUTOMATIC VEHICLE NUMBER IDENTIFICATION USING DIGITAL IMAGE PROCESSOR (DIP)
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Road accidents are one of the major causes of human deaths. Most of the deaths in accidents are due to damage to the head of the motorcycle riders. Among the different types of road accidents, motorcycle accidents are common and cause severe injuries. To reduce

Performance of Modified SRPT in Multiple Processor Multitask Scheduling
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In this paper we study the multiple- processor multitask scheduling problem in the deterministic and stochastic models. We consider and analyze M-SRPT, a simple modification of the shortest remaining processing time algorithm, which always schedules

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
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Extensive processor verification at the Register-Transfer Level (RTL) is crucial to avoid bugs. Therefore, simulation-based approaches are prevalent but they require efficient test generation methods to achieve a thorough verification. In this paper we propose an efficient

Implementation of 8-Bit RISC Processor
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A processor is a small chip that resides in computers and other electronic devices. Its basic job is to receive input and provide the appropriate output. While this seem like a simple task, modern processors can handle trillions of calculations per second. Modern CPUs often

Probing Many-body Localization with a Programmable Superconducting Quantum Processor
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In many-body localized (MBL) systems, entanglement propagates throughout the system despite the absence of transport. Early experiments have relied on population measurements to indirectly probe these entanglement dynamics. However, because the

Automatic Code Generation for Simultaneous Convolutional Kernels on Cellular Processor Arrays
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Recent developments in cellular processor array technology have produced new low power processor architectures for computer vision applications where one of the most fundamental computational operations is convolutional filters. In this thesis we develop a new frameworkIn ultra-high sampling rates, FFT is widely used for acoustic emission signals. In this manuscript, the effectual architecture of hardware is presented based on the execution of FFT due to radix-2 frequency decimation algorithm (R2DIF) and channeled method that

SUSTAINED RELEASE MULTI-PARTICULATES FORMULATION OF STEREO-SELECTIVE MOLECULE OF KETOPROFEN BY FLUID BED PROCESSOR
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The aim is to prepare sustained release multi-particulates dosage form of Dexketoprofen trometamol, which is the active isomer of ketoprofen. Utilization of active moiety with minimum drug dose and administration frequency sustainedrelease multi-particulatesThis paper proposes an integrated machine code monitor (iMCM) written in a hardware description language (HDL) and implemented in an FPGA together with a processor . The iMCM reconfigures monitor functions to be provided according to the verification progress of

Comparing MPI Passive Target Synchronization Schemes on a Non-Cache-Coherent Shared-Memory Processor
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MPI passive target synchronisation offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive

High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array
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Performance, storage, and power consumption are three major factors that restrict the use of machine learning algorithms on embedded systems. However, new hardware architectures designed with visual computation in mind hold the key to solving these bottlenecks

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor .
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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error

A Simple, Scalable Processorin-Memory Micro- processor for HPC Systems
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The Problem: There is a need for computer systems which can provide large amounts of computing power to solve problems with enormous requirements in terms of memory, computation, and communication resources. Examples of such problems are protein folding

A digital signal processor (DSP)-based system for embedded continuous-time cuffless blood pressure monitoring using single-channel PPG signal
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Dear editor, According to a World Health Organization (WHO) report, cardiovascular diseases accounted for the death of approximately 17 million people worldwide each year, ie, 37% of the annual global deaths . Therefore, the prevention and prediction of

EFFECT OF SPRAYING ORGANIC FERTILIZER, NANO PROCESSOR WITH BORON IN THE GROWTH AND PRODUCTIVITY OF CITRUS LIMON L. TREES
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The experiment was carried out in the main garden of the Horticulture Division, Al-Hindiya Station for the production of certified citrus seedlings, Karbala Governorate, Iraqi Ministry of Agriculture, during the season. The experiment included 9 treatments and three

Implementation of FFT Processor on FPGA
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Various processing applications such as video processing, audio processing, RF signal processing, image processing etc. include computation of transforms such as FFT. Computation of FFT sample is expensive in terms of speed, performance and throughput

3. VIRTUAL AND PHYSICAL MACHINES WITH MEGA- PROCESSOR CHIPS
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Many core computers are the current approach to the solution of computationally intensive problems. At the present day, many core mean 1000 but soon few 100000 or even more processing elements will be available on a desktop machine. One example of fine

Efficient Implementation of Spiking Neural Networks on the Loihi Neuromorphic Processor
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Recent developments of deep Artificial Neural Networks (ANNs) have pushed forward the state-of-the-art in the field of image recognition . However, the high power demand required by these networks when it comes to perform inference tasks on edge devices limits

New 19 Axes Single- Processor System, for Door Moldings Manufacturing
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The present paper describes a new technology for the manufacture of interior door moldings, in the spirit of Industry 4.0. A new manufacturing method is presented, using a single processor for all 19 axes numerically controlled. Thus, production costs are reduced

Bottom-up and top-down neuromorphic processor design: Unveiling roads to embedded cognition
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Together with the development of computers came the promise for exponential integration in silico, known as Moores law, and thus the dream to reach artificial cognition. As a first step toward bio-inspired computation, artificial neural networks (ANNs) take their roots in thePage 1. 1 XtenderContinuous Mixer (XCM) a novel polymer processor with recirculation Giuseppe Ponzielli*, Otto Mierka1 Date: May, 0 *Corresponding author e-mail address: g.ponzielli@nexxuschannel.com 1Present address: Ianus Simulation GmbH, 44227 Dortmund

Implementation of Massive MIMO Systems for 512-Point FFT Processor using VLSI Technology
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Substantial amount of latency in baseband is Massive Multiple Input and Multiple Output (MIMO) system. It establishes by new 5G technology and also by Orthogonal Frequency Division and Multiplexing -(OFDM). To proclaim latency of MIMO, a Fast Fourier

Hardware/Software Implementation of Image Processing Systems Based on ARM Processor
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In this paper we present a hardware/software platform for real-time image processing. We start with the creation of the hardware part based on the ARM processor (PS) with various drivers (PL) for reading, recording and displaying images. Using the SDK tool (Software

The ParaNut/RISC-V ProcessorAn Open, Parallel, and Highly Scalable Processor Architecture for FPGA-based Systems
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The paper presents a customizable, highly scalable, and RISC-V compatible processor architecture for FPGA-based systems. A key aspect of the ParaNut architecture is a special concept of parallelism, which combines advantages of SIMD vectorization and simultaneous

Implementation of OFDM with Programmable FFT Processor for Future 5G Communications
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The FFT (Fast Fourier Transform) processor plays a critical part in speed and power consumption of the Orthogonal Frequency Division Multiplexing (OFDM) communication system. This paper presents a high level implementation of a high performance FFT for

An FPGA-based Application-Specific Processor for Implementing the Exponential Function
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In this paper, we present a pipelined, high throughput single precision floating point implementation of the exponential function with a latency of 19 cycles. We also present the Application Specific Processor (ASP), a multiple memory architecture that increases memory Abstract The Sunway TaihuLight supercomputer has been installed for several years and many applications have been ported or built for TaihuLight. Initially most applications running on TaihuLight are with regular memory access patterns, such as dense linear

ESA Technical Note/Final Report (January 2020): CCN# 2: Support to MIPAS level 2 processor verification and validation-Phase F Report to MS6_2: L1v8/L2v8
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The detection of stratospheric trace gases plays a dominant role in a changing climate. Satellite measurements are essential for monitoring the distribution and trend of these species on a global scale. ESAs Environmental Satellite (ENVISAT) operated ten years

XTENDER, A NOVEL POLYMER MELT CO- PROCESSOR WITH RECIRCULATION, WITH AN APPENDIX ON RECIRCULATION FLOW IN COROTSE
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Xtender is a novel polymer melt co- processor with recirculation. The recirculation flow is a key factor in the mixing process. It allows for repeated passages of liquid particles across elongational wedgelike regions. Accordingly it is very important for the mixer to be able to

Three-phase Two-Leg Buck-Boost DC-AC Inverter with Differential Power Processor Unit
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Ahmed A. Hossam-Eldin 1 Ahmed A. Elserougi 2 Ahmed K. Abdelsalam 3 and 4Electrical Engineering Department, Faculty of Engineering, Alexandria University, Egypt 3 Electrical and Control Engineering Department, College of Engineering, Arab Academy for Science and