research project ideas-electronics-VLSI-VHDL
- VHDL approach to performance analysis of fuzzy logic controllers
- VHDL design and simulation of a fast beam loss interlock for TTF2
- Supporting VHDL Design for Air-Conditioning Controller Using Evolutionary Computation
- Array OL Descriptions of Repetitive Structures in VHDL
- Constrained Random Verification with VHDL
- Fundamentals of DIGITAL LOGIC with VHDL design
- Electromechanical modeling beyond VHDL
- Partitioning for multicomponent synthesis from VHDL specifications
- VHDL-AMS for mixed technology and mixed signal, an overview
- Assisting network intrusion detection with reconfigurable hardware
- VHDL-AMS in MEMS design flow
- OO-VHDL An Object Oriented VHDL
- Verification of COMBO6 VHDL Design
- VHDL modelling of a fuzzy co-processor architecture
- FPGAs Implementation of a digital IQ demodulator using VHDL
- Assessing the potential of multi-threaded VHDL simulation
- Proof theory and a validation condition generator for VHDL
- Objective VHDL-tools and applications
- Using a vhdl testbench for transistor-level simulation and energy calculation
- bject-Oriented Extensions to VHDL
- Energy-based characterization of microelectromechanical systems
- Experiences with VHDL Models of COTS RISC Processors in Virtual Prototyping for Complex System Synthesis
- Information flow analysis for VHDL
- A structured VHDL design method
- A Formalization of a Subset of VHDL in the Boyer-Moore Logic
- Implementing a petri net specification in a fpga using vhdl
- Fundamentals of DIGITAL LOGIC with VHDL design
- IAV- A VHDL methodology for FPGA implementation
- Static Analysis of VHDL Model Evaluation
- A model driven engineering design flow to generate VHDL
- A VHDL implementation of an on-board ACF application targeting FPGAs
- On the reuse of VHDL modules into systemC designs
- VHDL-based performance modeling and virtual prototyping
- An evolutionary approach to automatic generation of VHDL code for low-power digital filters
- Fault modeling and simulation using VHDL-AMS
- An object-oriented view of structural VHDL description
- Multi-level fault injections in VHDL descriptions: alternative approaches and experiments
- State machine design techniques for Verilog and VHDL
CSE PROJECTS