VLSI-VERY LARGE-SCALE INTEGRATION IEEE PAPERS AND PROJECTS-2020



Very large-scale integration is the process of creating an integrated circuit by combining millions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were widely adopted, enabling complex semiconductor and telecommunication technologies to be developed



Hybrid Discrete Hopfield Neural Network based Modified Clonal Selection Algorithm for VLSI Circuit Verification.
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Clonal selection algorithm and discrete Hopfield neural network are extensively employed for solving higher-order optimization problems ranging from the constraint satisfaction problem to complex pattern recognition. The modified clonal selection algorithm is a

A NEW VLSI ALGORITHM FOR A VLSI IMPLEMENTATION OF TYPE IV DST WITH LOW HARDWARE COMPLEXITY
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A new VLSI algorithm for a VLSI implementation with a low hardware complexity of type IV DST using only a single band correlation structure is presented. This approach is based on a new systolic array algorithm that uses an efficient restructuring of the type IV DSTInternational conference on Advances in VLSI and Embedded Systems (AVES-2019) . The conference aims to bring together leading researchers, engineers, and scientists in theLocal processing of machine learning algorithms like support vector machine (SVM) is preferred over the cloud for many real-time embedded applications. However, such embedded systems often have stringent energy constraints besides throughput and

DREAMPlace 2.0: Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs
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Modern backend design flow for very-large-scaleintegrated ( VLSI ) circuits consists of many complicated stages and requires long turn-around time. Among these stages, VLSI placement plays a fundamental role in determining the physical locations of standard cellsVLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named

ET19201 VLSI ARCHITECTURE AND DESIGN METHODOLOGIES PC 3 0 0 3 Objectives
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To give an insight to the students about the significance of CMOS technology To teach the importance and architectural features of programmable logic devices. To introduce the ASIC construction and design algorithms To teach the basic analog VLSI design

A Novel Approach for High Speed and low Power by using VLSI Domino Circuits
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As technology scales down beyond sub 22nm regime shorter channel effect dominate, single gate MOSFET face great challenge in nanometer while scaling which results in exponential increase in sub-threshold and gate oxide leakage current. To overcome non

Ant Colony Optimization for Power Efficient Routing in VLSI Design
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Due to the rapid advancement and growth in Very Large Scale Integrating VLSI design posed a number of challenges. With an increasing number of transistors in a chip, reducing power consumption is a very important goal and a major priority for designers to increase

A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI Architecture
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Convolutional encoding and viterbi algorithm are basic concepts of error correction method. Viterbi algorithm is one of decoding method for data error correction. In VLSI area, the design challenges are usually about its power, area consumption, speed, complexity, and

VLSI Implementation of Spin Transfer Torque-Magnetic Tunnel Junction-Perpendicular Magnetic Anisotropy (STT-MTJ-PMA) Structure
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The modern bio-inspired memory computing systems are suitable for implementation of Very Large Scale Integration circuits. They are also economically viable and also technologically feasible. The design of a bio-inspired computing system based on Spintronics is an

AN AREA EFFICIENT VLSI IMPLEMENTATION OF CARRY SELECT ADDER AND ALU TESTING
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Adders plays major role in multiplications and other advanced processors designs. Adders can be constructed for many numerical representations such as arithmetic and logical operation. The most adders operates on binary numbers. Among the different types of

VLSI architecture of a high speed Wiener Filter for video coding
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In the modern age, the use of video has become fundamental in communication and this has led to their use through an increasing number of devices. Thanks to the emerging media, such as social networks, streaming, internet and mobile devices in addition to the old media ABSTRACT CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power High-efficiency video coding (HEVC) is a latest video coding standard and the motion estimation unit is the most important block. The work presents the different types of Matching Criteria for Block-Based Motion Estimation technique in HEVC standard. HEVC requires fast

Design and VLSI Implementation of Low Latency IEEE 802.11 i Cryptography Processing Unit
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IEEE 802.11 i is the important security standard for wireless local area network, and it includes three security functions, which are WEP, TKIP, and CCMP, to provide the data confidentiality. In this paper, the effective cipher architecture of IEEE 802.11 i is developed to In this paper, an improved multi-objective optimization method, based on learning automata (called IMOLA), is proposed and its performance on the design of a variety of functional circuits is investigated. The most important feature of the proposed method is to provide a

Leakage Power Reduction in High Speed Domino Logic Circuits in Deep Submicron Technologies for VLSI Applications
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Leakage power and propagation delay are the two major challenges in VLSI design CMOS circuits in small scale technology. This paper proposes a novel technique for designing CMOS domino logic circuits with lector approach and modified inverter for the reduction in

Implementation of Massive MIMO Systems for 512-Point FFT Processor using VLSI Technology
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Substantial amount of latency in baseband is Massive Multiple Input and Multiple Output (MIMO) system. It establishes by new 5G technology and also by Orthogonal Frequency Division and Multiplexing -(OFDM). To proclaim latency of MIMO, a Fast Fourier

Improving Placement in VLSI Design Process via Hybridization of Simulated Annealing and Genetic Algorithms
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The simulated annealing algorithm is extensively used for cell placement in VLSI but its main downside is that it requires intensive computing to have optimum solutions in practical time. Genetic algorithms get trapped in local minima, however, they traverse the

Electronics and Communication Engineering
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CS824 Advanced Web Technologies 3 14.09.2020 Monday CS831 Web Mining CS833 Adhoc Networks 4 16.09.2020 Wednesday CS820 Foreign Language 1 ½ Hours (9.30 AM to 11.00 AM Electronics and Communication Engineering Sl. No. Date and Day Subject Code Subject

Design of high speed VLSI Architecture for FIR filter using FPPE
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Numerous applications based on VLSI architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and

VLSI Placement using Modified Parallel Simulated Annealing
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Today, placement is one of the most sensitive components of physical synthesis flow that have huge impact on the final performance of VLSI designs. However, it accounts for a significant part of the overall physical synthesis run-time. The placement problems are

A Greedy-Simulated Annealing approach for placement of VLSI circuits
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In this paper, we propose a heuristic approach for finding a near-optimal placement of VLSI circuits. Our algorithm starts with a greedy approach for providing an initial placement before starting the iterative simulated annealing improvement. Experiments have been carried out

Efficient FIR filter design using reconfigurable multipliers for VLSI Applications
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Hardware consumes most of the resources specifically for multiplication process compared to other ALU operations such as addition and subtraction. The most common latency factors like area, power and performance delay are generally controlled by conventional methods

VLSI Implementation in Biomedical Applications: A Review
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Recent disastrous incidents in health care system have disturbed the continuous process of care, leaving the health care sector in a state of emergency. The rise of trust flaw between patients and health bionetwork might hamper the aspired progress of the Indian health care

Optimization of Power Consumption in Cmos Vlsi Circuit Using Different Clusters
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Of late, there is a steep rise in the usage of handheld gadgets and high speed applications. VLSI designers often choose static CMOS logic style for low power applications. This logic style provides low power dissipation and is free from signal noise integrity issues. However Nonlinear sensors and digital solutions are used in many data acquisition system designs. As the input-output characteristic of most sensors is nonlinear in nature. Hence obtaining data from a nonlinear sensor by using an optimized device has always been a design

Performance Analysis of Squarely Packed Dimorphic MWCNT Bundle for High Speed VLSI Interconnect
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According to the demand of present era, carbon nanotubes are getting closer attention as VLSI high speed interconnects. This consequence drives us to conduct our research on the performance evaluation of different configurations of MWCNT bundle as interconnect based

FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures
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The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236 ns) implemented on FPGA A new test data compression scheme for circular scan architecture is proposed in this paper. A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency. In Abstract The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for

VLSI Arcitectures of Carry Skip Adders A Survey
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Adders are key building blocks in the arithmetic and logic units and hence increasing their speed and reducing their power consumption strongly affect the performance of digital circuits. There are many adder families with different delays, power consumptions, and area This paper presents the design and implementation of a low complexity and highly efficient configurable singular value decomposition (SVD) processor for 2 4 6 and 8 8 MIMO wireless communication systems. In order to minimize the area complexity while

Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution
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With the scaling down of the technology node, both power consumption, and supply noise are continuously increasing in modern VLSI designs. The emergent power supply noise through the power delivery network (PDN) can eventually degrade the chip timing in this paper we have designed faster power efficient sense amplifier for cmos sram using vlsi technology ie primarily schematic of sense amplifier is designed simulated using ads (advanced design system). The sense amplifier then implemented analyse at chip level

Digital Design issues in VLSI Design unit 3
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Here, clock at FF2 takes longer to succeed in as compared to the time taken by the clock to succeed in the FF1. Recall that the setup check means that the data launched should reach the capture flop at most setup time before the next clock edge. As evident within the below

Study and development of innovative strategies for energy-efficient cross-layer design of digital VLSI systems based on Approximate Computing
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I, Giulia STAZI, declare that this thesis titled, Study and development of innovative strategies for energy-efficient cross-layer design of digital VLSI systems based on Approximate Computing and the work presented in it are my own. I confirm that This work was done

A VLSI Implementation of Fast Binary to BCD Convertor using Complement Based logic design (CBLD)
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Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 times slower than binary arithmetic implemented in hardware. High performance low powerIn this paper, propose a high-performance and area-efficient VLSI architecture with 64-bit datapath for the PRESENT block cipher. The proposed architecture performs an integrated encryption/decryption operation for both 80-bit and 128-bit key lengths. The architecture is

Efficient and Design-Rule Aware Detailed Routing in VLSIDesign
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In VLSIrouting, we need to pack millions of vertex-disjoint Steiner trees into a graph with billions of vertices, while respecting a set of complicated design rules. Routing is solved in two or more stages: Global routing computes an approximate layout for each Steiner treeIn digital CMOS circuits, parametric yield improvement be achieved by reducing the variability of performance and power consumption of individual cell instances. In recent years, increasing demand of portable digital systems has led to rapid and innovative

Low Power VLSI Architecture for Encoder and Decoder
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the technology is improved by a network-on-chip (NoC) and the additional elements are added for opposing the dissipated power in ion subsystem. The acquiring of sample adaptive encoder architecture has been done as in-loop filtering block. The huge quantity of

HOW TO APPLY
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Dr BR Ambedkar National Institute of Technology Jalandhar 14401 Punjab Short Term Course on Low Power VLSI Design for Communication Systems and Networks (LVCSN20) (September 16th 20th2020) (One Week Duration) Low Power VLSI Design for

VLSI Circuits design using Resonant Rotary Clocking
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Resonant clocking technologies are nextgeneration clocking technologies that offer low or controllable-skew, low-jitter and multi-gigahertz frequency clock signals with low energy consumption. This paper describes a group of circuit partitioning, placement and

An Optimized VLSI Implementation of an IEEE 802.11 n/ac/ax LDPC Decoder
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This paper proposes optimization techniques for multi-Gbps low-power VLSI implementation of IEEE 802.11 n/ac/ax (WiFi) LDPC decoders. The IEEE 802.11 n/ac/ax standard features Quasi-Cyclic LDPC (QC-LDPC) codes with modular decoder structure composed of arrays

VLSI Based Energy-efficient Multipliers with double LSB operands
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In this paper, various multipliers are implementing for low power requirement and high speed. The efficiency can be implementing number mathematical approaches. The main focus is energy-efficient scheme for multiplying 2scomplementbinary numbers with two least

Preliminary Study of Different Multipliers in VLSI using VHDL
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Multiplier modules are common to many DSP applications. The fastest types of multipliers are parallel multipliers. Among these, the Array multiplier is the basic one. However, they suffer from more propagation delay. Hence, where regularity, high performance and low

Low Complexity of VLSI Computational Architectures for the ACT Techniques
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The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require floating point arithmetic, are multiplier intensive, and accumulate round-off Having worked in semiconductor design industry for over two decades, it was my strong desire to pass on the knowledge of system on chip design to the next generation. Therefore, I conceived the idea of writing a book on A Practical Approach to VLSI System on Chip

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and process data in real

Design and Analysis of 1-Bit SRAM
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Abstract SRAM (Static Random-Access Memory) is a memory component and is used in various VLSI chips due to its unique capability to retain data It does not require refreshing periodically which makes it the most popular memory cell among VLSI designers

High Speed Multi-Level Discrete Wavelet Transform Using Canonic Signed Digit Technique
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of Electronics and Comm Engg, SRK University, Bhopal, MP, India. Anu.sinha17@gmail.com, neeteshrkdf2010@gmail.com, bhartichourasia27@gmail.com Abstract-A few designs have been proposed for productive VLSI usage of 2-D DWT for continuous applicationsThis chapter (1) has been retracted by the Editors because it contains significant overlap with work published previously by Remya, VK, Parthiban, P., Ansal, V. et al.(2). The authors agree to this retraction.(1) Megha M., Ansal V.(2020) Performance Comparison of Semi-Z

3EC04: CMOS DIGITAL INTEGRATED CIRCUITS CREDITS 3 (LTP: 0, 0)
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Course Objective: The course intends to provide an understanding of the building blocks for microprocessor/microcontroller or digital VLSI circuit based on the MOS circuit 3. Douglas A. Pucknell and Kamran Eshraghian, Basic VLSI Design , 3rd edition, PHI Learning

DESIGN OF LOW POWER AND AREA EFFICIENT MULTIPLIERS USING ADVANCED GDI METHOD
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Several VLSI design techniques have been attempted to optimize the power and area occupied by the multiplier module, but there are very few design techniques that gives the required extensibility both in terms of power and area

3EC42: DIGITAL SYSTEMS DESIGN USING HDL CREDITS 4 (LTP: 0, 2)
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Unit No. Topics Teaching Hours 1. Introduction : History, About HDL, VLSI Design Flow, EDA Tools, Fundamental HDL Units, VLSI design Styles, Programmable Logic Devices, Standard Cell, Full- Custom Design, Basic details of Verilog, Comparison of Verilog and VHDL 08

A Design and Performance Analysis of 64-bit Multiplier based on Rounding Based Approximation technique
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multipliers which offer both of the following plan targets high speed, low power utilization, consistency of design and henceforth less zone or even mix of them in one multiplier in this way making them appropriate for different high speed, low power and minimal VLSI usage

An Open Source approach for ASIC Design Flow
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the most abstract architectures. Given the complexity of Very Large Scaled Integrated Circuits ( VLSI ) which is far beyond human ability, computers are increasingly used to aid in the design and optimization processes. It is no

DESIGN OF LOW POWER FULL ADDER USING ADIABATIC LOGIC
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VOLUME IX ISSUE IV, APRIL Page | 88 ABSTRACT VLSI technology permits the designers to put additional variety of gates in a single IC. so a to realize the moveable VLSI primarily based application circuits the action of power optimization is important