vlsi-very-large-scale integration IEEE PAPER, IEEE PROJECT
Low Cost VLSI Architecture for Proposed Adiabatic Offset Encoder and Decoder
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ABSTRACT A network-on-chip (NoC) improves the technology and the power dissipated starts to opposed with by the additional elements of the correspond ion subsystem. Sample adaptive encoder architecture has been acquired as a new in-loop filtering block. To get the
Analysis of Micro Inversion to Improve Fault Tolerance in High Speed VLSI Circuits
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With technology scaling, the reliability of circuits is becoming a rising concern. The emergence of logic errors in the field cause by faults escaping manufacturing testing, aging, single event upsets, or process variations is increasing. Conventional techniques for online
INVESTIGATION AND VLSI IMPLEMENTATION OF LINEAR CONVOLUTION ARCHITECTURE FOR FPGA BASED SIGNAL PROCESSING APPLICATIONS
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Convolution is a mathematical operation in signal processing applications which is used to predict the response of the system for a givenimpulse response. Focus on this area is stressed as it has various applications on fields like Digital Signal Processing (DSP), Digital This book describes the various test generation algorithms for testing crosstalk delay faults in VLSI circuits. Testing is an essential part of any integrated circuit manufacturing system. The problem of test generation is NP-complete problems, and it is becoming more and more
Survey on power optimization techniques for low power vlsi circuit in deep submicron technology
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ABSTRACT CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power
VLSI circuit configuration using satisfiability logic in Hopfield network
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Very large scale integration ( VLSI ) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural
Improved Testability Method for Mesh-connected VLSI Multiprocessors
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The problem of in-operation embedded hardware-level fault detection in mesh-connected VLSI multiprocessors is considered. A new approach to the multiprocessor test based on the mutual inter-unit checking is presented, which allows increasing the successful fault
A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications
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This paper proposes the implementation of a low power and high speed Vedic Divider based on ancient Indian Vedic mathematics. In this paper, an algorithm based on the ParavartyaYojayet is applied, throughout this sutra the propagation delay and power
Design of flip-flops for high performance VLSI applications using different CMOS technologies
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In this paper low power, high speed design of SET, DET, TSPC and C2CMOS Flip-Flop are designed and analysed. As these flip flop have a small area and low power consumption they can be used in various applications like digital VLSI clocking system, buffers, registers
A Novel High Speed Simulated Annealing Algorithm for Non-Slicing VLSI Floorplanning using B*-Tree Representation
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Objective: To optimise area, interconnecting wirelength and dead space of very large scale integration non-slicing floorplan with high computation speed using evolutionary algorithm intelligently. Methods/Statistical Analysis: Floorplanning is one of the most important steps in
Hybrid Discrete Hopfield Neural Network based Modified Clonal Selection Algorithm for VLSI Circuit Verification.
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Clonal selection algorithm and discrete Hopfield neural network are extensively employed for solving higher-order optimization problems ranging from the constraint satisfaction problem to complex pattern recognition. The modified clonal selection algorithm is a
VLSI Design of a Fast Pipelined 8x8 Discrete Cosine Transform
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This paper presents a Very Large Scale Integrated ( VLSI ) design and implementation of a fixed-point 8x8 multiplierless Discrete Cosine Transform (DCT) using the ISO/IEC 23002-2 algorithm. The standard DCT algorithm, which is mainly used in image and video
Digital Design issues in VLSI Design unit 3
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Here, clock at FF2 takes longer to succeed in as compared to the time taken by the clock to succeed in the FF1. Recall that the setup check means that the data launched should reach the capture flop at most setup time before the next clock edge. As evident within the below
Simulated Annealing algorithm for VLSI floorplanning for soft blocks
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In the VLSI physical design, Floorplanning is the very crucial step as it optimizes the chip. The goal of floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between the modules, optimize the area of the floorplan and High-efficiency video coding (HEVC) is a latest video coding standard and the motion estimation unit is the most important block. The work presents the different types of Matching Criteria for Block-Based Motion Estimation technique in HEVC standard. HEVC requires fast
Performance Analysis of Mixed Carbon Nano Tubes as VLSI Interconnects
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Abstract Background/Objectives: This paper presents various possible structures of Mixed Carbon Nano Tubes bundle which consists of different topology of Single Wall Carbon Nano Tubes (SWCNTs) and Multi wall Carbon Nano Tubes (MWCNTs). Methods/Statistical With shrinking sizes of devices and increasing chip densities, circuits have become so fast, compact, and inaccessible that the use of conventional methods based on mechanical probe has become limited and inadequate. The conventional test methods or the
A Review Paper on Multiplier Algorithms for VLSI Technology
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In the era of digitalization, it is required to increase the speed of digital circuits while reducing area and power consumption. In any digital system, multiplication is a key element. One of the important parameter which affects the performance of entire system is
Sampled Analog VLSI Architectures for Real Time Signal Processing Applications
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This dissertation presents the design of sampled analog VLSI architectures that can be applied to real time signal processing. These architectures consume minimum hardware than their equivalent digital architectures and eliminate the need of data converters by
Performance Analysis of SISO-OFDM Architecture for Wireless Applications using VLSI Technology
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Novel technologies have started emerging as an evolution of wireless communication standards, and corresponding low cost devices are key to follow this trend in order to achieve better quality of service (QoS) and support large amount of users that can
Model-order reduction of VLSI circuit interconnects via a Laguerre representation
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Abstract The VLSI (Very Large Scale Integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompanied by digital blocs. With this
Implementation of VLSI Binary64 Division with Redundant Number Systems
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Binary division usually use redundant representation of partial remainders and quotient digits. VLSI realizations of digit-recurrence allows for fast carry-free computation of the next partial remainder, and the latter leads to reduce number of the required divisor multiples
Much More than Moore-a journey from VLSI to disease biomarkers
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Chairperson, Centre for Nano Science and Engineering, Indian Institute of Science (IISc), Bengaluru, for his work on the design of novel biosensors based on his research in biochemistry, and gas sensors that push the performance limits of existing metal-oxide
High-Level Synthesis Based VLSI Architectures for Video Coding
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Abstract High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard. Emerging applications like free-viewpoint video, 360degree video, augmented reality, 3D movies etc. require standardized extensions of HEVC. The standardized extensions of
Trends and challenges in VLSI at Device level: Carbon Electronics
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The MOSFET is a four terminal device with source (S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently connected to the source terminal so making it a three terminal device like field effect transistor. The MOSFET is very far the most common
VLSI design of a novel area efficient architecture of metric compression turbo decoding
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The turbo code is one of the most attractive forward error correction codes, which can provide near-optimal bit error rates (BERs) of Shannons limit. Due to this feature in this paper to improve the memory in the decoding architecture a new technique named NII
Multi objective inclined planes system optimization algorithm for VLSI Circuit Partitioning
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In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the dynamic of sliding motion along a frictionless inclined plane. In this work, modules
VLSI IMPLEMENTATION OF UNIVERSAL SERIAL BUS NRZI ENCODING AND DECODING
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In this paper the hardware design approach for implementing of universal serial bus NRZI encoding and decoding in chip. Communication plays an important role in day to day life. The information or data is transmitted through various techniques and line coding is one of
A Survey of VLSI Architectures for Hamming Code Algorithm
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In the present innovations, correspondence has numerous applications, and in each field the information is encoded at the transmitter, exchanged over a correspondence channel and got at the recipient after information is decoded. Amid the procedure of transmission in a
A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and process data in real
VLSI IMPLEMENTATION OF IMAGE THRESHOLDING ALGORITHMS
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In document image processing, binarization plays a significant part especially in degraded document images. Among various thresholding algorithms, local image thresholding algorithm plays a better binarization performance for degraded document images. However
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