vlsi-very-large-scale integration ieee papers 2019-2019-IEEE


Model-order reduction of VLSI circuit interconnects via a Laguerre representation
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Abstract The VLSI (Very Large Scale Integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompanied by digital blocs. With this

Implementation of VLSI Binary64 Division with Redundant Number Systems
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Binary division usually use redundant representation of partial remainders and quotient digits. VLSI realizations of digit-recurrence allows for fast carry-free computation of the next partial remainder, and the latter leads to reduce number of the required divisor multiples

Much More than Moore-a journey from VLSI to disease biomarkers
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Chairperson, Centre for Nano Science and Engineering, Indian Institute of Science (IISc), Bengaluru, for his work on the design of novel biosensors based on his research in biochemistry, and gas sensors that push the performance limits of existing metal-oxide

High-Level Synthesis Based VLSI Architectures for Video Coding
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Abstract High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard. Emerging applications like free-viewpoint video, 360degree video, augmented reality, 3D movies etc. require standardized extensions of HEVC. The standardized extensions of

Trends and challenges in VLSI at Device level: Carbon Electronics
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The MOSFET is a four terminal device with source (S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently connected to the source terminal so making it a three terminal device like field effect transistor. The MOSFET is very far the most common

VLSI design of a novel area efficient architecture of metric compression turbo decoding
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The turbo code is one of the most attractive forward error correction codes, which can provide near-optimal bit error rates (BERs) of Shannons limit. Due to this feature in this paper to improve the memory in the decoding architecture a new technique named NII

Multi objective inclined planes system optimization algorithm for VLSI Circuit Partitioning
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In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the dynamic of sliding motion along a frictionless inclined plane. In this work, modules

VLSI IMPLEMENTATION OF UNIVERSAL SERIAL BUS NRZI ENCODING AND DECODING
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In this paper the hardware design approach for implementing of universal serial bus NRZI encoding and decoding in chip. Communication plays an important role in day to day life. The information or data is transmitted through various techniques and line coding is one of

A Survey of VLSI Architectures for Hamming Code Algorithm
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In the present innovations, correspondence has numerous applications, and in each field the information is encoded at the transmitter, exchanged over a correspondence channel and got at the recipient after information is decoded. Amid the procedure of transmission in a

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and process data in real

VLSI IMPLEMENTATION OF IMAGE THRESHOLDING ALGORITHMS
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In document image processing, binarization plays a significant part especially in degraded document images. Among various thresholding algorithms, local image thresholding algorithm plays a better binarization performance for degraded document images. However





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