ENGINEERING RESEARCH PAPERS

vlsi and low power vlsi research paper 2014





Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity.
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(MTL) equations is of fundamental importance for the design and signal integrity verification of interconnections in VLSI systems. It is well established that the critical issue is the efficient and accurate electrical characterization of the MTLs through the determination of their per-

Development of Low Temperature Oxidation Process Using Ozone For VlSI
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Abstract: With decreasing size of MOS transistor the thickness of gate oxide (SiO2) is reaching in regime where it is just 2-3 atomic layers thick about 1 to 1.5 nm thick because of thin oxide layers there is direct tunnelling of charge carriers through gate oxide, and the

Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences
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Abstract The tutorial offers attendees an opportunity to bridge the semiconductor ICs/system industry with the biomedical and pharmaceutical industries. The tutorial will first describe emerging applications in biology and biochemistry that can benefit from advances in

Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithm.
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The Gaussian surface for full-net extraction ? Fast but inaccurate, able to extract full-chip. ? Has tunable accuracy and is scalable to large cases. [1] M. Kamon and R. Iverson, High-accuracy parasitic extraction, in EDA for IC Implementation, Circuit Design,

Energy Efficient Advanced Low Power CMOS Design to reduce power consumption in Deep Submicron Technologies in CMOS Circuit for VLSI Design
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Abstract: Low power has emerged as a principal theme in today's electronic industry. Energy efficiency is one of the most critical features of modern electronic systems designed for high speed and portable applications. Reduction of power consumption makes a device more

A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficientVLSI architecture
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Abstract:A novel reduced-complexity soft-input soft-output minimum mean square error detection algorithm for MIMO systems together with an area-throughput efficient VLSI architecture is described. A detailed comparison to related work is presented. The

Advanced Symbolic Analysis for VLSI Systems
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Symbolic analysis is an intriguing topic for VLSI design. Traditional symbolic analysis is typically concerned with deriving exact or approximate analytic expressions of analog circuit performance in terms of circuit parameters. Such symbolic expressions give clear

AN OPTIMAL FLIP FLOP DESIGN FOR VLSI POWER MINIMIZATION.
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Abstract The power consumption is critically important in modern VLSI circuits especially for low-power applications. Optimization of power at the logic level is one of the most important tasks to minimize the power. Among logic components, latches and flip-flops are

VLSI Architecture for Implementing Kaiser Bessel Window Function Using Expanded Hyperbolic CORDIC Algorithm
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Abstract-Windowing techniques have been widely used for preprocessing of samples before fast Fourier transform (FFT) in real time spectral analysis to minimize spectral leakage and picket fence effect. Among all popular window functions, Kaiser-Bessel window is an

Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors
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Abstract:A computational complexity analysis of matrix inversion used in soft-input soft- output minimum mean square error (MMSE) MIMO detectors and a comprehensive literature comparison of corresponding VLSI implementations are presented. They indicate that the

Phase Locked Loop using VLSI Technology For Wireless Communication
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Abstract: Literature survey of Phase Locked Loop reflects that many researchers have applied different techniques like digital and analog simulation by applying mathematical/logical relations to design the Phase Locked Loop (PLL). Researchers have

Evaluation and Comparison of Single-Wall Carbon Nanotubes and Copper as VLSIInterconnect
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G Dhillon, K Singh Evaluation, 2014 ijireeice.com
Abstract: The work in this paper addresses the capabilities and performance of single wall carbon nanotube (SWCNT) bundles as interconnects for applications in VLSI circuits. The carbon nanotube (CNT) bundles have potential to provide an alternate solution for the

A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSIDesign
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Abstract:A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each subbus. Unlike ordinary BI circuits using invert-lines, TBIC does not

Predict VLSI Circuit Reliability Risks Using Neural Network
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Abstract This paper describes the challenges faced in predicting the reliability of very large scale integration (VLSI) circuits. Currently, lots of trial-and-errors are still needed for the parameters selected to develop a neural network prediction model, whose result is with a

Trace-Based Post-Silicon Validation for VLSI Circuits
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This book includes, but is not limited to, the research work on post-silicon validation during the author Xiao Liu's Ph. D. study. Post-silicon validation is an emerging research field, and limited publications are available to summarize the state of the art on it. Interested readers

Power reduction in digital VLSI circuits
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Abstract The increased use of Portable electronics devices such as cellular phones, notebook and computers has made power dissipation an important design metric in modern microelectronics. Portable devices that operate using a battery have limited energy

Analysis of VLSI Based Induction Motor Speed Control using Auto Tune PID Controller
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Abstract: This is the review work for VLSI based Induction Motor Speed Control using Auto Tune PID controller. The present paper suggested stand alone control device for industrial induction motor speed control. PID tuning is proposed using successive approximation

EE-382M VLSI–II OFF-CHIP DRIVERS/RECEIVER DESIGN SPRING 2014
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A REPORT ON LOW POWER VLSI CURCUIT DESIGN
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Abstract We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. The most important factor in any system design is power. Low power became a major factor where power dissipation has become as important

System Design for Encoding and Decoding to Minimize the Crosstalk in VLSI Circuits
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Abstract: In the growing up world many technologies are growing faster and faster as they are becoming smaller and smaller, one such is the very large scale integrated design-VLSI. Many challenges are faced in VLSI, one of them is the crosstalk occurrence. Global buses

Optimization Techniques for Low Power VLSI Circuits
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Abstract: Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low

VLSI Based 1-D ICT Processor for Image Coding
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Abstract: The Integer Cosine Transform (ICT) presents a performance close to Discrete Cosine Transform (DCT) with a reduced computational complexity. The ICT kernel is integer- based, so computation only requires adding and shifting operations. This paper presents

CMOS VLSI Implementation of Adders with Low Leakage Power
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Abstract: Due to the semiconductor technology revolution, portable consumer electronic products are made with more features. The power dissipation factor is important since those systems are built with plenty of transistors. As the sizes of the transistors shrink and the

Implementation of BDDs by Various Techniques in Low Power VLSI Design.
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Abstract:Power has become an important design parameter in today's ultra low submicron digital designs as found. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters, voltage regulators

BACKTRACK INPUT VECTOR ALGORITHM FOR LEAKAGE REDUCTION IN CMOS VLSIDIGITAL CIRCUIT DESIGN
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Abstract A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics
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Abstract In the past, most of the research and development efforts in the area of CMOS and IC's are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the

CMOS VLSI Design of Low Power Comparator Logic Circuits
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Abstract As the demand of portable consumer electronic products increases rapidly and the chip size decreases, designers are facing many challenges towards the circuit area and power. Decades ago, engineers worried about the speed of operation of the system. They

VLSI IMPLEMENTATION OF RC4 STREAM CIPHER USING HARDWARE PIPELINING
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Scale Integrated (VLSI) design of high performance Ron's Code 4 (RC4) stream cipher using hardware pipelining to achieve high throughput, high speed and optimum area without compromising the cryptographic security. We have achieved the high throughput

An Efficient VLSI Architecture for Removal of Impulse Noise in Images
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Abstract Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, an efficient VLSI implementation of Adaptive Rank Order Filter (AROF) for removal of impulse noise is proposed. The algorithm

Wireless Cellular Communication Using 100 Nanometers Spintronics Device Based VLSI
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Abstract: Rapid progress in the miniaturization of the semiconductor electronic devices leads towards chip features smaller than 100 nanometers in size. This revolution offers opportunities for developing a new generation of device incorporating standard

A Novel VLSI Architecture of a Weighted Average Method based Defuzzifier Unit
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Abstract:In fuzzy control systems, fuzzification and defuzzification are two important procedures. Defuzzification plays an important part in the implementation of a fuzzy system, since the fuzzy data is not suitable for real time applications; it needs to be converted into

A Study on Various Data Mining Algorithms Pertaining to VLSI Cell Partitioning
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Abstract VLSI Cell Partitioning plays a substantial part in VLSI physical design. The task of designing integrated circuits is multifaceted, as modern circuits have a very huge number of modules. It is very much essential to split the circuit into a smaller and meeker logic blocks

Analysis of Utility Theory on VLSI Cell Placement
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Abstract: This paper focuses on the employment of utility theory for decision making under risk and uncertainty. Further, we have also investigated the efficiency of the three types of utility curves namely Conservation Man, Average player and the Gambler. The utility

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems
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MC Bhuvaneswari 2015 Springer This book describes how evolutionary algorithms (EA) such as genetic algorithms (GA) and particle swarm optimization (PSO) can be used for solving multiobjective optimization problems in the area of embedded and VLSI systems design. This book is written primarily

Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region
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L Kou 2014 etd.library.vanderbilt.edu As technology scales, power consumption has become a major concern in circuit design [HAP+ 05]. In the early history of CMOS, the scaling of the supply voltage was in accordance with the scaling of the transistors in order to maintain constant electric fields in the device.

Simulation Analysis and Performance of the Reactive Components of MOS Structure Towards Small Size Vlsi Circuits
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M Dababneh, IAZ Qatawneh Middle-East Journal of Scientific Research, 2014 idosi.org
Abstract: In this research thin film layers have been prepared at alternate layers of resistive and dielectric deposited on appropriate substrates to form four–terminal RY-NR network. If the gate of the MOS structures deposited as a strip of resistor film like NiCr, the MOS

Design and Implementation of Neural Network Based circuits for VLSI testing
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KP Sridhar, B Vignesh, S Saravanan, M Lavanya 2014 idosi.org
Abstract: Artificial Neural Network (ANN) plays a vital role in biologically inspired microcircuits, which is also known as the new trend of Very Large Scale Integration (VLSI) involvement of silicon based neurons. This paper proposes a new design methodology in

VLSI Implementation and Performance Evaluation of Universal Modulator using CORDIC Algorithm for Digital Communication Applications
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P Nagaraju, K Babulu, V Sailaja 2014 piserjournal.org
Abstract: Today's communication systems and software radio based applications required fully digital Antennas, consisting of fully programmable circuit with digital modulators and demodulators. A basic communication system's modulator modulates the amplitude,

Test Data Compression Architecture for Lowpower VLSI Testing
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B Karthik, TVUK Kumar, A Selvaraj World Applied Sciences Journal, 2014 idosi.org Accepted: Jan 24, 2014; Published: Jan 27, 2014
Abstract: With the ever increasing integration capability of semiconductor technology, today's large integrated circuits requires an increasing amount of data for testing which increases test time and elevated

Analysis of Clustering Techniques in VLSI Cell Partitioning
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Abstract Circuit partitioning plays a dominant role in VLSI physical design of chips. In this paper the newly proposed rank based k-medoid clustering algorithm is discussed, in order to partition the combinational circuit based on their interconnection distance among cell

A VLSI Architecture for H. 264/AVC Variable Block Size Motion Estimation
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DM Tung, TLT Dong Journal of Automation and Control Engineering Vol, 2015 joace.org
Abstract:In this paper, we propose an efficient VLSI architecture for variable block size motion estimation (VBSME) in H. 264/AVC to reduce the hardware cost and latency. The proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of

Parallel Architecture for the VLSI Implementation
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A Geetha World Applied Sciences Journal, 2014 idosi.org Accepted: Jan 25, 2014; Published: Jan 28, 2014
Abstract: Error detection and correction plays a very important role in data communication. Various codes such as convolutional and block codes are available for the purpose of error detection and correction. Among the

CROSSTALK NOISE REDUCTION USING WIRE SPACING IN VLSI RC GLOBAL INTERCONNECTS
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A Agra, V Maheshwari Journal of Electron Devices, 2014 jeldev.org This paper presents a closed form 2p crosstalk noise model for on-chip VLSI RC interconnects. It considers a case when unit step input is applied to the aggressor which is adjacent to the victim net and producing crosstalk noise effect over it. In the next section

Graphene and its Dopants used as a Transistor in VLSI Circuits
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S KHAN, S GUPTA, D SINGH 2014 computerscijournal.org
Abstract Graphene, a sheet of carbon atoms arrayed in a honeycomb pattern, could be a better semiconductor than silicon. Due to many such properties graphene has been under study as a alternative substance used, rather then graphite and silicon in transistors. But

Cryptography Based On Hash Function BLAKE 32 in VLSI
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G Sunny, C Saranya IJCSNS, 2014 paper.ijcsns.org
Abstract An important commodity in the world of Electronic Communication is information. The protection of authenticity and integrity of information is necessary to achieve a secure communication between communicating parties. Electronic security is becoming

System Design for Encoding and Decoding to Minimize the Crosstalk in Vlsi Circuits
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M Surumbarkhuzhali, PR Sujae World Applied Sciences Journal, 2014 idosi.org Accepted: Jan 28, 2014; Published: Jan 29, 2014
Abstract: In the growing up world many technologies are growing faster and faster as they are becoming smaller and smaller, one such is the very large scale integrated design-VLSI. Many challenges are faced in VLSI,

Vlsi Implementation of Evolvable Pid Controller
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M Surumbarkhuzhali, PR Sujae World Applied Sciences Journal, 2014 idosi.org Accepted: Jan 28, 2014; Published: Jan 29, 2014
Abstract: It is known that the application of PID controller span from small industry to high technology industry. Due to PID controllers' widespread use in industry, tuning procedures for them are always a topic of interest. In

LOW POWER VLSI COMPRESSORS FOR BIOMEDICAL APPLICATIONS.
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Abstract We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 90nm technology. Hybrid-CMOS design style makes use of various CMOS logic style circuits to build new full adders with

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE.
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NR Divya, K Kannadasan ICTACT Journal on Image Video 2014 ictactjournals.in
Abstract Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data

Logic Complexity Reduction and VLSI Architecture for Image Compression Using Conventional Adders
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NR Divya, K Kannadasan 2014 arph.in
Abstract-In last few decades, portable multimedia devices are attracts more consumers all the time with their features of low power and large digital storage. Most of the people are extending their requirements which may give little difficulty to designer to handle the

Vlsi Based Accident Information and Car Security System
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S Khuzhali Middle-East Journal of Scientific Research, 2014 idosi.org
Abstract: VLSI based Accident information and car security system deals with the concern of saving the victim, who gets trapped in accident and also about the car security. Accident of the car is detected using pressor sensors which are fixed in car. Accident information to

Effective Clustering Algorithms for VLSI Circuit Partitioning Problems
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Abstract In this article, the effective circuit partitioning techniques are employed by using the clustering algorithms. The technique uses the circuit netlist in order to cluster the circuit in partitioning steps and it also minimizes the interconnection distance with the required

VLSI decoding architectures: flexibility, robustness and performance
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Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated

VLSI ARCHITECTURE OF MIMO DETECTOR USING FIXED COMPLEXITY SPHERE DECODING
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Abstract Fixed Sphere Decoding is a near optimum tree search detection technique for the spatial multiplexing scheme. The algorithm performs a fixed number of operations to detect the signal independent of the noise level and channel conditions. In this paper, a

Lightweight VLSI Design of Hybrid Hummingbird Cryptographic Algorithm
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N Arora, Y Gigras International Journal of VLSI and Embedded Systems- ijves.com
Abstract Due to drastic increase in e-commerce, there is need for real time implementation of light weight cryptographic algorithms to be used in low cost smart devices such as RFID tags, smart cards, wireless sensor network, PDA's etc. Hummingbird is a

WIDEBAND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS
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This paper presents an analog VLSL circuit for implementation of Artificial Neural Networks (ANNs). The building blocks of the proposed circuit include Differential voltage current controlled source (DVCCS), Super MOSFET and Differential voltage controlled voltage

VLSI Implementation of Parallel Prefix Subtractor using Modified 2's Complement Technique and BIST Verification using LFSR Technique
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M Kumari, V Gupta, GK Jindal ijsr.net
Abstract: Parallel prefix Subtractor is the most flexible and widely used for binary addition/subtraction. Parallel Prefix Subtractor is best suited for VLSI implementation. No any special parallel prefix Subtractor structures have been proposed over the past years

VLSI Detailed Routing
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R Piersiak rafalku.com
Abstract:Detailed Routing takes the channels and switchboxes created by the global routing and wires the nets to the terminals. It is a methodic approach, efficiently wiring each region one-byone, ensuring that all previous routed regions are unaffected by the current

An Efficient VLSI Computation Reduction Scheme in H. 264/AVC Motion Estimation
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Abstract:-The variable block sizes motion estimation in H. 264 is key technique to remove inter-frame redundancy. This technique not only requires huge memory bandwidth but also its computation complexity is higher. Therefore, this paper proposes one efficient sub-pixel

SENSITIVITY ANALYSIS OF VLSI INTERCONNECT OUTPUT SIGNAL
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Abstract: Interconnect parameters play an important role in signal propagation in VLSI systems. In the paper we present the sensitivity analysis to parameters of typical on-chip interconnects for the step and ramp response. In the paper we show also the sensitivity to

VLSI Implementation and Analysis of Parallel Adders for Low Power Applications
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S Arunprasath, A Karthick, D Dhineshkumar 2014 d.researchbib.com
Abstract:Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified

A VLSI Implementation of Fast Addition Using an Efficient CSLAs Architecture
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S Saleem, AM Reddy ijircce.com
Abstract: Carry Select Adder (CSLA) is a fast adder used in dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. However, the Regular

EFFICIENT VLSI ARCHITECTURE USING DIT-FFT RADIX-2 AND SPLIT RADIX FFT ALGORITHM
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MJ Rashmi, GS Biradar, M Patil ijtre.com
Abstract: FFT has wide use in communication for processing the data being exchanged. Hence it is important to develop high-performance FFT architecture to meet the requirements of real time and low cost in many different systems. Efficient VLSI architecture based on

E3 239 Advanced VLSI Circuits High-Performance SRAM Design
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R Rao chips.ece.iisc.ernet.in Page 1. E3 239 Advanced VLSI Circuits 43, no. 10, 2008 Hanson, S. et al., The Phoenix Processor: A 30pW Platform for Sensor Applications , VLSI Symposium, 2009 Chang, L., et al., Stable SRAM Cell Design for the 32 nm Node and Beyond , VLSI Symposium, 2005

Concepts of Primitive Polynomial and Galois Field in Designing More Randomize PN Sequence Generators for Maximum Fault Coverage in Modern VLSI
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P Shrivastava, P Purohit, PS Tanwar, H Shrivastava ijisme.org
Abstract:This paper deals with the vital role of primitive polynomials for designing PN sequence generators. The standard LFSR (linear feedback shift register) used for pattern generation may give repetitive patterns. Which are in certain cases is not efficient for

Design and Implementation of Low Power High Speed VLSI DSP System for Multirate Polyphase Interpolator
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RM Rewatkar, SL Badjate ijeee.in Multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP

SIMULTANEOUS ROUTING AND BUFFER INSERTION ALGORITHM FOR MINIMIZING INTERCONNECT DELAY IN VLSI LAYOUT DESIGN
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In deep submicron fabrication technology, transistors can now switch much faster, but wire resistances are now larger, and delay due to wires can exceed gate delay. Consequently, the interconnect delay is the dominant factor in the construction of wire routing in very

Design of Low Cost Image Scaling Processor Using Single Line Buffer Based on VLSIArchitecture
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R Rubini, V Gopi ijareeie.com
Abstract: Image scaling is the process of resizing a digital image. It is one of the most important methods used in various applications such as sharpening of an image, image zooming, preserving edge structures in an image and so on. This paper proposes an

RESOURCEFUL FAST DHT ALGORITHM FOR VLSI IMPLEMENTATION BY SPLIT RADIX ALGORITHM
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M Tamilselvi, MP Gomathi, A Lakshminarayanan ijret.org
Abstract A new very large scale integration (VLSI) algorithmic rule for a 2N-length discrete hartley transform (DHT) that may be expeditiously enforced on a extremely standard and parallel VLSI design having a regular structure is given. The DHT algorithmic rule may be

VLSI Design of a Parallel MCMC-based MIMO Detector with Multiplier-Free Gibbs Samplers
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Abstract:Little consideration has so far been dedicated to the investigation of the implementation complexity of stochastic detectors for multi-antenna (MIMO) systems although they promise communications performance close to max-log detection for certain

TEST DATA COMPRESSION FOR LOW POWER TESTING OF VLSI CIRCUITS
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J Robert Theivadas, R Vijayaraghavan ijetae.com VLSI circuits are Test data volume and excessive test power. Among the many different compression coding schemes proposed till now, the CCSDS (Consultative Committee for Space Data Systems) lossless data compression scheme is one of the best. This paper

Vlsi Implementation Of Multiple Error Recovery In Tmr System Using Scan-Chain
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R Athira, VJA Karthick iosrjournals.org
Abstract: Scan chain based multiple error recovery technique for a triple modular redundancy (TMR) system is used to detect and correct multiple errors in TMR systems. This method uses scan chain flip flops to detect and correct faulty modules. The errors are

An Extensive Review on Reversible Logic in VLSI
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Abstract:As of late reversible rationale has risen as a guaranteeing processing model for provisions in scattering less optical registering, low power CMOS, quantum figuring, and so on. In reversible circuits there exist a coordinated mapping between the inputs and the

Design and Analysis of CMOS Multiplier and EEAL Multiplier for Low Power VLSI Application
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Efficient Adiabatic Logic (EEAL) is proposed. In adiabatic logic, which dissipates less power than static CMOS logic, have been adiabatic circuits called energy efficient adiabatic logic introduced as a promising new approach in low power circuit design. The adiabatic

VLSI IMPLEMENTATION OF REAL TIME SPEECH RECOGNITION
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Abstract-The main aim of this project is to find the authenticationof user'svoice based on FPGA voice processing. Voice samples of authorized users will be trained and stored in VLSI hardware. Whenever the user speaks in front of microphone, the incoming voice

A Genetic Approach for Area Reduction in VLSI Layout
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Abstract Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit. Integrated circuit is a collection of one or more gates fabricated on a

Low Power Multi Bit Flip Flops Design for VLSI Circuits
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Abstract: In this paper we present a power optimization technique to reduce clock power by using multi bit flip flop method. We have proposed the several techniques to overcome the problems of flip-flops replacement without timing and placement capacity constraints

AN EFFICIENT DESIGN OF VLSI ARCHITECTURE FOR FAULT DETECTION USING ORTHOGONAL LATIN SQUARES (OLS) CODES
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Abstract:-Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm

VLSI DESIGN PROCESS FOR LOW POWER DESIGN METHODOLOGY USING RECONFIGURABLE FPGA
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Abstract Modern digital processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the

Design of Storage Element for Low Power VLSI System
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Abstract-The storage elements are major power consuming component in VLSI system. The power reduction of storage element leads to reduction of global power consumption of VLSI system. In this paper, a Proposed single edge triggered (SET) and a Proposed double

VLSI Implementations of Compressive Image Acquisition Using Block Based Compression Algorithm
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Abstract: In this research paper consists of compressing the images within each pixel before the storage processes, hence the size of the memory gets reduced. This can be done by the proposed method namely block based compression algorithm which uses the differential

Comparative Analysis and Efficient VLSI Implementation of FIR Filter
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M Kadam, K Sawarkar, S Mande ijareeie.com
Abstract: In this paper, we present suitable design optimization for area-delay efficient implementation of finite impulse response (FIR) filter on Field Programmable Gate Array (FPGA). Architectural optimization done in MATLAB/Simulink environment, Hardware

Design of a Chip Area Efficient Low Drop-Out Voltage Regulator Using VLSI
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N Ahmed, GD Dalvi ijirs.com
Abstract: The usage of the battery power devices in today's global village has become pervasive and indispensable in almost every walk of life. The thrust is towards reducing the number of battery cells, required to decrease cost and size, while minimizing quiescent

Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology
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RV Tambat, SA Lakhotiya 2014 inpressco.com
Abstract This paper enumerates low power, high speed design of SET, DET, TSPC and C2CMOS Flip-Flop. As these flip flop topologies have small area and low power consumption, they can be used in various applications like digital VLSI clocking system,

An Efficient Model for Design of 64 Bit Parallel Prefix VLSI Adder
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GJP Babu, S Dharani, A Satish ijeert.com
Abstract: Most of the manipulations are done based on the addition operations. To make the system effective and high speed a parallel adder plays an important role. With the help of a parallel prefix addition process we can achieve better results. In this paper a 64 bit parallel

EE 458 Analog VLSI
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H Bajwa webeditor.bridgeport.edu Objective: The objective of the course is introduction of the fundamental concepts required for the creative and successful design of analog VLSI circuits. We will discuss basic transistor models and layout techniques for the design of analog integrated circuits. We

A Survey of VLSI Techniques for Power Optimization and Estimation of Optimization
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N Sharma, M Kaur ijetae.com
Abstract-With the advancement in compact, portable and high-density micro-electronic devices and systems, the power dissipated in very large scale integrated (VLSI) design circuits has become a critical concern. Accuracy and efficiency in power estimation

VLSI Realization of Area efficient FIR Filters
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N Bhardwaj, V Gupta iosrjournals.org
Abstract: Arithmetic circuit Multiplication happens oftentimes in finite impulse response (FIR) filters, quick Fourier transforms, distinct trigonometric function transforms, convolution, and to avoid wasting vital temporal order consumption of a VLSI style. Here, we have a tendency

VLSI Implementation of Image Sensor for Spatial Filtering
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K Siva¹, SPS Kumar iaster.com
Abstract A low-complexity adaptive scaling algorithm is proposed for the implementation of 2-D image scaling applications. a less complexity, less memory requirement, and high performance algorithm is proposed for Very Large Scale Integration implementation of an

An Efficient Distributed Tree Structure Modelling for VLSI circuits
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M Kavicharan, NS Murthy, NB Rao europment.org
Abstract:In this paper a closed-form matrix rational model for the computation of finite ramp responses of distributed Resistance Inductance Capacitance (RLC) tree in VLSI circuits is presented. This model allows the numerical estimation of delay in distributed RLC tree.

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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G Knagge project.sigpromu.org
Abstract:Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

Polynomial Time Algorithms for the 3-Dimensional VLSI Routing in the Cube
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Abstract. In previous works some polynomial time algorithms were presented for special cases of the 3-Dimensional VLSI Routing problem. Solutions were given to problems when all the terminals are either on a single face (SALP-Single Active Layer Problem) or on two

Optimization of Power Consumption in VLSI Circuit
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MPK Gupta, J Kaliraman iosrjournals.org
Abstract: Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to

VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION
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J Moses, D Selvathi enggjournals.com
Abstract:Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points.

VLSI Implementation of Variable Length Radix-2^ 5 for Cognitive Radio System
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JJ Babu, KE Prelly ijirset.com
Abstract-Cognitive Radio System (CRS) is a radio system which is aware of its operational and geographical environment, established policies, and its internal state. It is able to dynamically and autonomously adapt its operational parameters (sub carrier mapping)

A LOW POWER CMOS VOLTAGE MODE SRAM CELL FOR HIGH SPEED VLSI DESIGN
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U PAVANI, S KUNTAMALLA iisthub.com
Abstract: In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic

VLSI Design and Performance Analysis of Different Full Adder Topologies at 0.25 Micrometer Technology Node
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AS Rajput, R Parashar ijarcet.org
Abstract:Full Adders are the most important components in digital design which not only perform addition operations, but also helpful in calculating several other functions such as subtraction, multiplication and division operations. Different types of adders are frequently

Modeling and Performance Analysis of Fuzzy Logic Controller Based Direct Torque Control ofVLSI Fed Three
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S Prabaharan, P RameshBabu, N Vijayasarathi ijirset.com
Abstract:This manuscript deals with fuzzy logic controller based Direct Torque Control (DTC) of three phase Induction Motor Drive using MATLAB and its toolbox SIMULINK. The Direct Torque Control of VSI fed Induction Motor is implemented with the help of

Issues of Optimization Techniques Targeting Low Power VLSI Circuits Design
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MS Tara, MS Dilshad ijaceee.com
Abstract:In this paper the issues and state-of-the-art optimization methods that target low power dissipation in VLSI circuits Design. Optimizations at the circuit, logic, architectural and system levels are considered. The issues related to the Power dissipation in the design

Error Control Coding Architecture Using VLSI Implementation
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NK Shankar ijaesit.org
Abstract-Viterbi algorithm is widely used as a decoding technique for convolutional codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power.

Performance Analysis of VLSI Based Multilevel Inverter
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Abstract:This paper compares two different topologies of three phase inverter (ie diode clamped followed by cascade H-bridge) which includes five level and seven level inverters. The selection of topology and control techniques may vary according to power demands

VLSI and Algorithms for High-Speed Arithmetic
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AA Liddicoat, MJ Flynn 171.64.73.62
Abstract Area, latency, and process technology have a considerable impact on the cost- performance characteristics of floating point unit (FPU) design. Quantitative design metrics allow the FPU designer to make knowledgeable tradeoffs. Additionally, new algorithms

Design and implementation of a Multiplier-Less VLSI Architecture using Wavelet Filter Banks
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Abstract:Wavelet based signal processing incorporating Hilbert transform pair is proved to be more efficient by many authors. The multiplier-less VLSI based architecture of wavelet filter bank for biomedical applications is being proposed in this project. The proposed

Power-Efficient VLSI Implementation of A Feature Extraction Engine for Spike Sorting in Neural Recording and Signal Processing
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T Wu, Z Yang ece.nus.edu.sg
Abstract:This paper presents a power-efficient VLSI implementation of a feature extraction engine for the applications of real-time spike sorting. Traditional method like principal components analysis (PCA) works in a batch mode by diagonalizing the covariance matrix

Clock Tree Power Optimization of Three Dimensional VLSI System with Network
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M Saranya, S Mahalakshmi, PS Devi ijirset.com
Abstract: The proposed method is based on minimum-cost maximum-flow formulation to globally determine the tree topology, which maintains load balance and considers the wirelength between pulse generators and pulsed latches. Experimental results indicate

Comparative Analysis of Improved Domino Logic Based Techniques for VLSI Circuits
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S Kamde, S Badjate, P Hajare oaji.net
Abstract-In modern VLSI design, Domino logic based design technique is widely used and in which power ignites the speed of circuit. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.

System On Chip: Performance Analysis Of VLSI Based Networking System
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P Chenna, B Panda, A Putta ijecct.org
Abstract--The swell in the numeral of cores that can be incorporated on a distinct chip has forced the designer to use computer system concepts for design of System on Chip (SoC). The supplementary is of multiple protocols being used in the diligence at present. For

An Implementation of Image Compression using VLSI Architecture
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Y Jyotsna, B Sravya, KP Satamraju ijettjournal.org
Abstract:This paper proposes a novel progressive image compression algorithm using the wavelet transform. Wavelets are effective in capturing directional information in images using a flexible set of basis functions and filtering process that are elongated and

Algorithm to color a Circuit Dual Hypergraph for VLSI Circuit
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B Gogoi, B Kalita ijcsit.com
Abstract:Line-of-sight graph is used to check the number of short circuit testing needed to test a printed circuit board. This paper presents a simple algorithm based on some assumptions to put color in a circuit dual hypergraph of a VLSI circuit. The structures of

VLSI Implementation of Orthogonal Space Time Block Coding (OSTBC) Based High Throughput Multiple Modes MIMO
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A Deepa, C Palanchur ijettjournal.org
Abstract: Space Time Block Coding, in a wireless communication system transferring of data over Long Term Evolution downlink channel using multiple antennas at the transmitter and receiver ends which improve reliability of data transfer. In data transferring, data are first

VLSI Implementation of Multi Mode SoC FMA 128 bits
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MM Mahendra aijcse.com
Abstract-The floating point arithmetic is complex and its complexity increases after the repeated floating point operation as a result the performance of field-programmable gate arrays (FPGAs) used for floating-point applications is decreased due to this floating point

VLSI Architecture for DCT Based On High Quality DA
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U Sharma, T Verma, R Jain erpublication.org
Abstract:Discrete Cosine Transform (DCT) is the major building blocks in an image and video compression system, which can be achieved using various specialized algorithms. It is also being used in various standardized coding schemes. Such as JPEG, MPEG-2, and

VLSI IMPLEMENTATION OF NOISE CANCELLATION IN AUDIO SIGNALS USING LMS AND RLS ALGORITHMS
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P RADHIKA ISO 9001: 2008 Certified Journal ijerss.com
Abstract In this paper the eminence of the Recursive Least Squares (RLS) algorithm over LMS algorithms is provided. This algorithm is designed to provide similar performance to the LMS algorithm while reducing the computation time. This paper represents the

VLSI Architecture of High Performance Turbo Decoder for Wireless Sensor Networks
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JMMS Gunasekar, S Jagadish, R Karthik ijareeie.com
Abstract: The sensor nodes of a wireless sensor network (WSN) are typically required to maintain sporadic but reliable data transmissions for extended periods of time. However, in applications the sensor nodes have to be small, preventing the use of bulky batteries. The

A VLSI Architecture for Color Space Transformation Module in an Object Tracking System
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R Mishra cryptonindia.com
Abstract-The increasing demand for real time image and video processing applications has paved the way for innovation of efficient VLSI architectures for these systems. In this paper an efficient color space transformation algorithm is implemented in VHDL (VHSIC

A NEW APPROACH FOR DELAY AND LEAKAGE POWER REDUCTION IN CMOS VLSICIRCUITS
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R Singh, ASM Tripathi ijarse.com
Abstract In the nanometer range design technologies dynamic power dissipation is very important issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards down in respect of size and achieving higher operating speeds. We

Low-Power and Low-Area Dual Dynamic Node Hybrid Flip-Flop Featuring Efficient Embedded Logic for Low Power CMOS VLSI Circuits Using 120nm
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M Pelleti, TK Murthy, K Neelima ijetae.com
Abstract:In this paper, a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFFELM) based on DDFF are introduced. The DDFF offers power and area reduction when compared to the conventional flip-flops. The main aim of

VLSI Implementation of DES TDES Algorithm with Cipher Block Concept
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KV Chethan Kumar, S Sujatha ijese.org
Abstract:This paper presents FPGA implementation of the DES and Triple-DES with improved security against power analysis attacks. This is programmed in verilog. DES TDES is basically used in various cryptographic applications and wireless protocol

FPGA Design of Reconfigurable Binary Processor Using VLSI
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S Mahalakshmi, MK Duraipandian ijirset.com
Abstract:Binary image processing is a powerful tool in many image and video applications. In this paper we proposed efficient hardware architecture of Binary image processor for low power applications and also propose an Efficient Majority Logic Fault Detection algorithm

A Real Time Implementation of an Image Scaling Processor Using VLSI Technique
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FA Azeez, M AnandKumar ijesrt.com
Abstract Image scaling is a very important technique and has been widely used in many image processing applications. In applications where the scaling process must be performed at the display rather than at the CPU OR GPU, dedicated hardware

Memristor Mos Content Addressable Memory Operating At 32-Nm for Future High Performance Search Engine Using VLSI Technology
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PP Harne, SK Nanda ijirs.com
Abstract: In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is

An Efficient VLSI Implementation of Lossless ECG Encoder Design
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VK KC, HS Veena ijsr.net
Abstract: An efficient VLSI implementation of a lossless electrocardiogram encoding circuit is designed for remote monitoring service. To reduce the wireless transmission power and the amount of storage data, an efficient lossless encoding algorithm had been built for the

Power Efficient Design of BILBO using Various Sequential Elements for Low power VLSIApplications (Basic 5T-transistor and 5T-with MTCMOS)
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P Nagarajan, K Nithya ijesrt.com
Abstract This paper enumerates low power design of BILBO (Built-In-Logic-Block-Observer) using Basic 5T-TSPC clocked latch and 5T-TSPC (MTCMOS) clocked latch. The clocked latches are basic building block to design the BILBO. The clocked latches consumes more

Performance Analysis of High Performance Energy Efficient Logic Styles in VLSI
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V Vijayan, SS Pillai ijcsits.org
Abstract:This paper presents a comparative study of high performance energy efficient logic styles in VLSI circuits. It has a keen role in the field of VLSI circuits. As the VLSI technology is upgrading this energy efficient logic styles are also upgrading. This logic

Stacked Keeper with Body Bias: A New Approach to Reduce Leakage Power for Low PowerVLSI Design
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KN Bhargav, A Suresh, G Saini cryptonindia.com
Abstract:In this paper we present a technique named as stacked keeper with body bias (SK- BB). It uses stack effect to existing sleepy keeper technique along with body bias for ultra low static power consumption. A 4-bit CMOS adder circuit is designed using existing

VLSI Based Design of Low Power and Linear CMOS Temperature Sensor
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P Jain, PK Jain ijergs.org.managewebsiteportal.com
Abstract:Complementary Metal Oxide Semiconductor (CMOS) temperature sensor is introduced in this paper which aims at developing the MOSFET as a temperature sensing element operating in sub-threshold region by using dimensional analysis and numerical

A NOVEL APPROACH ON PSO IN VLSI ROUTING
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K Madhavi ijarece.org
Abstract-The performance of very large scale integration (VLSI) circuits predominantly depends on routing of interconnected circuits. The chief problems in the design of VLSI layouts are wire sizing, buffer sizing and buffer insertion. This technique exits to improve

SYNTHESIS AND SIMULATION OF HYPERBOLIC TANGENT ACTIVATION FUNCTION USING HYBRID APPROMATION IN VLSI
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Abstract:Hardware implementation of neural network has major application in analog and digital areas. The major building blocks for implementation are adder, multiplier and non- linear activation function. A major challenge is faced in the implementation of activation

A 3.52 GSps Throughput VLSI Architecture of I/Q Imbalance Compensator for 60 GHz Communication System
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C Wang, X Fu, Y Yan ieee.org.hk
Abstract:This paper presents an I/Q imbalance compensator which can support the throughput rate of 3.52 GSps and improve the signal-to-interference ratio (SIR) from 10.1 dB to 33 dB for a 60-GHz communication system in the IEEE 802.11 ad standard. The

LOW-TRANSITION TEST PATTERN GENERATION FOR MINIMIZING TEST POWER IN VLSICIRCUITS USING BIST
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PINVCU BIST ijireeice.com
Abstract: Any Integrated circuit (IC) manufactured by the semiconductor manufacturing company contains test circuit and the circuit under test (CUT). The test circuit is used to test the correct functionality of the CUT and which is called Built In Self Test (BIST). This Built

Improving Message Authentication by Integrating Encryption with Hash function and its VLSIImplementation
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M Meenakumari, G Athisha ijireeice.com
Abstract: Presently more techniques are available for improving secure data communication. Public and private key encryption algorithms are available to provide confidentiality. Encryption techniques provide origin authenticity by using shared secret key. Advanced

Survey on Low Power VLSI Testing Techniques
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S Bhojwani, S Udvanshi coronapublication.com
Abstract: Power dissipation has become a major design objective in many application areas, such as wireless communications and high performance computing, thus leading to the production of numerous low-power designs. At the same time, power dissipation is also

Crosstalk Avoidance in VLSI Interconnects Using Bus Encoding Method
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B Venkataramana, PK Kumar, PS Reddy International Journal of ripublication.com
Abstract In current Deep Sub Micron (DSM) Technology, interconnects play an important role in overall performance of the chip. Scaling reduces the distance between interconnects which increases the coupling capacitance, propagation delay, power dissipation and

VLSI Design of ECG QRS Complex Detection using Multiscale Mathematical Morphology
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SV Gopeka, L Murali, T Manigandan cryptonindia.com (VLSI) based electrocardiogram (ECG) QRS complex detector for wearable devices in body sensor networks. Multiscale Mathematical Morphology (MMM) is a method used to suppress background noise and baseline wandering from original ECG signal. The major

Impact of Hybrid Pass-Transistor Logic (HPTL) on Power, Delay and Area in VLSI Design
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G Sivaiah, T Kishore, KV Kumar, S Mitra, D Gautam International Journal ijmer.com
Abstract: Power reduction is a serious concern now days. As the MOS devices are wide spread, there is high need for circuits which consume less power, mainly for portable devices which run on batteries, like Laptops and hand-held computers. The Pass-

Implementation of Hyperbolic Tangent Activation Function in VLSI
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IMEVD Student, T SACOE 2014 ijarcst.com
Abstract This work presents the implementation of Artificial Neural Network (ANN) chip, which can be designed to implement certain functions. Usually designing of neural networks is done using software tools in the computer system. The neural networks designed off-

An Optimized Successive Interference Cancellation for CI-Based Multiuser Detection UsingVLSI Implementation Strategy
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Abstract: In this project, we proposed variable rate carrier interferometry multicarrier code division multiple access (CI/MC-CDMA) multiuser transceiver that achieves a data rate of minimum 1Gbps equivalent to the 4G standard of IEEE. Multiple Carrier-Code Division

Sleepy Keeper Approach for Common Source CMOS Amplifier for Low-Leakage Power VLSIDesign
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MA Hafeez, A Shaw ijesrt.com
Abstract As the scaling goes deep into nano-meter range the leakage power dissipation has overtaken the dynamic power dissipation in VLSI circuits. The demand for low power consumer electronic gadgets which are portable reliable and with a long battery life has

Multiplier Based and Canonical Signed Digit Based VLSI Architecture for Discrete Wavelet Transformation
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P Barsaiyan, M Hinnwar ijaiem.org
Abstract THE DISCRETE wavelet transform (DWT) is a multi resolution analysis tool with excellent characteristics in the time and frequency domains. Through the DWT, signals can be decomposed into different sub-bands with both time and frequency information. The

VLSI Architecture Design Parameters and Tools: A Review
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KS Bhullar, HK Kang ijetae.com
Abstract:Electronic Systems are necessity of everyday lives. It's an integral part in financial networks, communication systems, power plants systems and personal computers solutions. Electronic systems network is increasingly based on complex and hybrid VLSI (Very Large

A Low Hardware Complex Bilinear Interpolation Algorithm of Image Scaling for VLSIImplementation
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Abstract In this brief, a low-complexity, low-memoryrequirement, and high-quality algorithm is proposed for VLSI implementation of an image scaling processor. The proposed image scaling algorithm consists of a sharpening spatial filter, a clamp filter, and a bilinear

VLSI IMPLEMENTATION OF BACK PROPAGATED NEURAL NETWORK FOR SIGNAL PROCESSING
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Abstract:-Mainly due to the rapid advances in integration technologies, large-scale systems design-in short, due to the advent of VLSI Technology, the number of applications of integrated circuits in high-performance computing, telecommunications, and consumer

VLSI Architecture for MB-OFDM Transmitter
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Abstract:(MB-OFDM) Multi-Band Orthogonal Frequency Division Multiplexing is a suitable solution for implementation of high speed data transmission in ultra wideband spectrum by dividing the spectrum into available multiple bands. In MB-OFDM system the most

Design of 2-D DWT VLSI Architecture for Image Compression
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TS Chandraraju, S RadhaKrishnan iieng.org
Abstract:In this paper, a new data access scheme for the computation of lifting 2-D DWT (Discrete Wavelet Transform) using systolic arrays with block processing is suggested. From DG (dependence graph) linear systolic array is directly derived. For parallel and pipeline

Design of area efficient chip layout of fractional N-phase locked loop using VLSI technology. A
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AV Manwatkar, VB Padole ijireeice.com
Abstract: In communication system power is one of the most important parameter. Power is the amount to function or generating out energy. This means that it is a way of measuring how fast a function can be carried out. So power has become one of the most important

DHT ALGORITHM FOR HIGHLY PARALLEL IMPLENTATION OF VLSI ARCHITECTURE
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SN Shagufa, SS Anjum, BR Reddy erpublication.org
Abstract:A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be

Power Consumption of CIC Decimation Filter with Sharpened Zero Rotation Using VLSITechnique
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R Mononisha, G Brindha internationaljournalssrg.org
Abstract The CIC decimation filter with zero rotation and compensation section was developed and presented in this paper. The magnitude response of the filter with various decimation factors considering different stages were estimated and compared with the

HIGH SPEED AND LOWER HARDWARE COMPLEXITY VLSI ARCHITECTURE FOR LIFTING BASED DISCRETE WAVELET TRANSFORM
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K Kokulavani, M Mohankumar 2014 ijcsmc.com
Abstract:A high speed and lower hardware complexity 2-D discrete wavelet transform architecture has been proposed. Previous DWT architectures are based on the modified lifting scheme or the flipping structure. Folded architecture method has been adopted. In

VLSI Implementation analysis of area and speed in QSD and Vedic ALU
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B Bishnoi, G Jangid ijaers.com
Abstract:Arithmetic operations in digital signal processing applications suffer from problems including propagation delay and circuit complexity which may occupy larger area. We have two high performance methods among all ALU circuitry. First one is QSD and

Performance Analysis Of DSTN Structured Full Adders In Low Power VLSI Circuits
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Abstract:the growing market of mobile, batterypowered electronic systems (eg, cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. As density and complexity of the chips continue to increase, the

VLSI Implementation of Enhanced AES Cryptography
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Abstract: Advanced Encryption Standard (AES) is a Federal Information Processing Standard (FIPS) and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is

A LFSR based Binary Numeral System Using CMOS VLSI
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Abstract The integrated chip manufacturing technology has made an evaluation by shrinking the size of a chip and enhancing its better performance. Shrinkage of chip introduces problems including heat dissipation and power consumption. Binary numeral

A Decimal Floating Point Arithmetic Unit for Embedded System Applications using VLSITechniques
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Abstract: With the growing popularity of decimal computer arithmetic in scientific and commercial financial and internet based applications, hardware realization of decimal arithmetic algorithm is gaining more importance. Hardware decimal arithmetic unit serve

HIGH THROUGHPUT DECODING ARCHITECTURE FOR BINARY CODE OPERATION AND MITIGATING THE SOFT ERRORS IN VLSI DEVICES
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N VINOTHINI ijisaer.com
Abstract--We present an approach to designing capacity-approachinghigh-girth lowdensity parity-check LDPC) codes thatare friendly to hardware implementation and compatible withsome desired input code structure defined using a prototype. The

SPEED ENHANCEMENT IN 64-BIT PARALLEL PREFIX VLSI ADDER USING AN EFFICIENT METHOD
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Abstract:High speed computation is an important parameter to evaluate the overall performance of computing devices. To manipulate the addition operations with more speed and accuracy parallel prefix addition is a better method. In this paper a 64-bit parallel

An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility
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Abstract:-This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional

VLSI Implementation of Reduced Resource Allocation for Modified Carry Look-Ahead Adder
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Abstract:With the increase in the VLSI technology level the system level designs are becoming too complex by effect of brutal design of low level complex design. The reduction in resources allocated to implement the system contributes to the significant decrease in

VLSI Power Efficiency, Leakage, Dissipation and Management Techniques: A Survey
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Abstract:Modern processor and controlling systems are using increasingly sized-up on- chip cache memory. With this there has been significant increase in leakage power consumption. This reason, accounts for overall and cache power management research

VLSI Based Image Zooming Application by a Novel Adaptive Edge Enhancement Technique
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M Saranya, V Meenakshi ijareeie.com
Abstract: In this paper, an adaptive edge enhancement technique is proposed for two- dimensional (2-D) image scaling application. The anticipated image scaling algorithm consists of an edge detector, bilinear interpolation and sobel filter. The bilinear

TD-AMS PROCESSING FOR VLSI IMPLEMENTATION OF LDPC DECODER
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Abstract An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On

Power and Area Efficient Error Tolerant Adder Using Pass Transistor XOR Logic in VLSICircuits
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SS Kumar, V Muralidharan, S Raja ijarcet.org
Abstract:In adders the truncation and round off errors cannot be ignored. A new type of adder that is error tolerant adder (ETA) is proposed to tolerate those errors and to attain low power consumption. To rectify the errors in adders error tolerant adder (ETA) is proposed

VLSI Based Fluid Flow Measurement Using Constant Temperature Hot Wire Anemometer
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A Singh, PK Jain ijergs.org
Abstract:The performance of a hot-wire anemometer configuration is affected by variation in the fluid temperature. The classical temperature compensation techniques in such anemometers employ two sensors. The performance of a temperature-compensated

Power Efficient Vlsi Architecture For High Throughput And Low Area Implementation Of Lifting 2-D Dwt
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JMD Babu, MB Sudha iosrjournals.org
Abstract: In this paper a new VLSI architecture was implemented for computation of lifting twodimensional (2-D) discrete wavelet transform (DWT). This structure was data transposition free and it was implemented by using linear systolic array which is derived

Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications
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T Schumann downloads.hindawi.com This is a special issue published in VLSI Design. All articles are open access articles distributed under the Creative Commons Attribu- tion License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

High Performance Adder Circuit In Vlsi System
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M Sentamilselvi, P Mahendran 2014 ijteee.org
Abstract: In VLSI system. The integrated circuit design has important role. The various parameters are considering for design the circuit. The important parameters are power and delay. The different tools are used to perform the operation. However, here the

Implementing the L8 segment Voronoi diagram in CGAL and an application in VLSI pattern analysis
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Abstract:In this work we present a CGAL (Computational Geometry Algorithm Library) implementation of the line segment Voronoi diagram under the L8 metric, building on top of the existing line segment Voronoi diagram under the Euclidean (L2) metric. CGAL is an

A Vlsi Architecture With Data Dependency Detector For Image Interpolation And Impulse Denoising
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Abstract-In this paper a low complexity, less memory requirement and high performance data dependency algorithm is proposed for very large scale integration (VLSI) implementation of an image scaling and impulse denoising processor. This algorithm

Analysis of VLSI Pacemaker Designs: A review
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A Kaur ijritcc.org
Abstract:In this paper, we have reviewed different types of intelligent control systems designs that are used to regulate the heart rate by the use of pacemaker. These system works in a closed loop way and works on the theory that the heart is powered by the

Development of EDA Tool with Easy Plugin for New VLSI Algorithms
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Abstract:An EDA tool has been developed with an emphasis on teaching-learning of various algorithms related to graph theory and VLSI design. The tool provides basic graphics operations, coordinate control and a command processor. Extensions to the

VLSI Design of Fast Addition Using QSD Adder for Better Performance
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Abstract: The high speed digital circuits became more prominent with incorporating information processing and computing. Arithmetic circuits play a very critical role in both general-purpose and application specific computational circuits. The modern computers

VLSI IMPLEMENTATION OF DISTRIBUTED ARITHMETICFIR FILTER
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S Jayashri, P Saranya 2014 arph.in
Abstract:Hardware implementation of FIR Filter has major applications in Analog and Digital areas. In this project a multiplier less fir filter is designed and implemented based on a distributed arithmetic algorithm. The proposed work achieves the reduction of hardware

Comparative Analysis of CMOS Mixers in 45NM VLSI Technology
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Abstract Frequency translation in a system is performed by a non-linear device known as a mixer. A substantial discussion has been provided for several CMOS circuit configurations which are currently used to realize a frequency mixing operation with more emphasis on

A Novel Delay and Overshoot Estimation model for VLSI Global Interconnects
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Abstract:In this paper, we propose a novel, simple and accurate delay and overshoot estimation model for VLSI Global Interconnects, based on new matrix Pade-type approximant (MPTA). This model reduces the computational complexity by considering

DESIGN AND IMPLEMENTATION OF SLEEP TRANSISTOR BASED LOW POWER CMOS DESIGN FOR SUBMICRON VLSI TECHNOLOGIES
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low power vlsi 2014



A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSIDesign
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Abstract:A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each subbus. Unlike ordinary BI circuits using invert-lines, TBIC does not

Energy Efficient Advanced Low Power CMOS Design to reduce power consumption in Deep Submicron Technologies in CMOS Circuit for VLSI Design
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AS Gaur, J Budakoti Energy, 2014 ijarcce.com
Abstract: Low power has emerged as a principal theme in today's electronic industry. Energy efficiency is one of the most critical features of modern electronic systems designed for high speed and portable applications. Reduction of power consumption makes a device more

A REPORT ON LOW POWER VLSI CURCUIT DESIGN
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K Saurabh, P Mani Management, 2014 ijermt.org
Abstract We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. The most important factor in any system design is power. Low power became a major factor where power dissipation has become as important

Optimization Techniques for Low Power VLSI Circuits
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M Jasmin Middle-East Journal of Scientific Research, 2014 idosi.org
Abstract: Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low

Implementation of BDDs by Various Techniques in Low Power VLSI Design.
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PK Sharma, M Kumar International Journal on Recent Trends in 2014 searchdl.org
Abstract:Power has become an important design parameter in today's ultra low submicron digital designs as found. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters, voltage regulators

CMOS VLSI Design of Low Power Comparator Logic Circuits
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Abstract As the demand of portable consumer electronic products increases rapidly and the chip size decreases, designers are facing many challenges towards the circuit area and power. Decades ago, engineers worried about the speed of operation of the system. They

CMOS VLSI Implementation of Adders with Low Leakage Power
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Abstract: Due to the semiconductor technology revolution, portable consumer electronic products are made with more features. The power dissipation factor is important since those systems are built with plenty of transistors. As the sizes of the transistors shrink and the

LOW POWER VLSI COMPRESSORS FOR BIOMEDICAL APPLICATIONS.
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Abstract We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 90nm technology. Hybrid-CMOS design style makes use of various CMOS logic style circuits to build new full adders with

Design and Analysis of CMOS Multiplier and EEAL Multiplier for Low Power VLSI Application
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Efficient Adiabatic Logic (EEAL) is proposed. In adiabatic logic, which dissipates less power than static CMOS logic, have been adiabatic circuits called energy efficient adiabatic logic introduced as a promising new approach in low power circuit design. The adiabatic

Design of Storage Element for Low Power VLSI System
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Abstract-The storage elements are major power consuming component in VLSI system. The power reduction of storage element leads to reduction of global power consumption of VLSI system. In this paper, a Proposed single edge triggered (SET) and a Proposed double

Power Efficient Design of BILBO using Various Sequential Elements for Low power VLSIApplications (Basic 5T-transistor and 5T-with MTCMOS)
free download

Abstract This paper enumerates low power design of BILBO (Built-In-Logic-Block-Observer) using Basic 5T-TSPC clocked latch and 5T-TSPC (MTCMOS) clocked latch. The clocked latches are basic building block to design the BILBO. The clocked latches consumes more

Stacked Keeper with Body Bias: A New Approach to Reduce Leakage Power for Low Power VLSI Design
free download

Abstract:In this paper we present a technique named as stacked keeper with body bias (SK- BB). It uses stack effect to existing sleepy keeper technique along with body bias for ultra low static power consumption. A 4-bit CMOS adder circuit is designed using existing

Survey on Low Power VLSI Testing Techniques
free download

Abstract: Power dissipation has become a major design objective in many application areas, such as wireless communications and high performance computing, thus leading to the production of numerous low-power designs. At the same time, power dissipation is also

Sleepy Keeper Approach for Common Source CMOS Amplifier for Low-Leakage Power VLSIDesign
free download

Abstract As the scaling goes deep into nano-meter range the leakage power dissipation has overtaken the dynamic power dissipation in VLSI circuits. The demand for low power consumer electronic gadgets which are portable reliable and with a long battery life has

Performance Analysis Of DSTN Structured Full Adders In Low Power VLSI Circuits
free download

Abstract:the growing market of mobile, batterypowered electronic systems (eg, cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. As density and complexity of the chips continue to increase, the

Issues of Optimization Techniques Targeting Low Power VLSI Circuits Design
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Abstract:In this paper the issues and state-of-the-art optimization methods that target low power dissipation in VLSI circuits Design. Optimizations at the circuit, logic, architectural and system levels are considered. The issues related to the Power dissipation in the design

VLSI Implementation and Analysis of Parallel Adders for Low Power Applications
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Abstract:Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified

A LOW POWER CMOS VOLTAGE MODE SRAM CELL FOR HIGH SPEED VLSI DESIGN
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Abstract: In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic

Low-Power and Low-Area Dual Dynamic Node Hybrid Flip-Flop Featuring Efficient Embedded Logic for Low Power CMOS VLSI Circuits Using 120nm
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Abstract:In this paper, a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFFELM) based on DDFF are introduced. The DDFF offers power and area reduction when compared to the conventional flip-flops. The main aim of

VLSI Based Design of Low Power and Linear CMOS Temperature Sensor
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Abstract:Complementary Metal Oxide Semiconductor (CMOS) temperature sensor is introduced in this paper which aims at developing the MOSFET as a temperature sensing element operating in sub-threshold region by using dimensional analysis and numerical

Low-Power VLSI Implementation in Image Processing using Programmable CNN
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Abstract The low power CMOS implementation is based on a combination of MOS transistors operating in di erent modes: weak and stronginversion. We propose, MOS transistors operating in the lateral bipolar mode. This combination has enabled a VLSI

Design and Implementation of Low Power High Speed VLSI DSP System for Multirate Polyphase Interpolator
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Multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP

TEST DATA COMPRESSION FOR LOW POWER TESTING OF VLSI CIRCUITS
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VLSI circuits are Test data volume and excessive test power. Among the many different compression coding schemes proposed till now, the CCSDS (Consultative Committee for Space Data Systems) lossless data compression scheme is one of the best. This paper

Low Power Multi Bit Flip Flops Design for VLSI Circuits
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LA Prabha, S Joy ijircce.com
Abstract: In this paper we present a power optimization technique to reduce clock power by using multi bit flip flop method. We have proposed the several techniques to overcome the problems of flip-flops replacement without timing and placement capacity constraints

VLSI DESIGN PROCESS FOR LOW POWER DESIGN METHODOLOGY USING RECONFIGURABLE FPGA
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Abstract Modern digital processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the

An Efficient VLSI Implementation of Low Power AES–CTR
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Abstract: This paper delineates an efficient VLSI architecture implementation in order to increase the throughput and security using Advanced Encryption standard (AES) algorithm. The existing architecture depicts the blocks like Sub Bytes, Shift Rows, Mix Column, and

LOW-TRANSITION TEST PATTERN GENERATION FOR MINIMIZING TEST POWER IN VLSICIRCUITS USING BIST
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Abstract: Any Integrated circuit (IC) manufactured by the semiconductor manufacturing company contains test circuit and the circuit under test (CUT). The test circuit is used to test the correct functionality of the CUT and which is called Built In Self Test (BIST). This Built

DESIGN AND IMPLEMENTATION OF SLEEP TRANSISTOR BASED LOW POWER CMOS DESIGN FOR SUBMICRON VLSI TECHNOLOGIES
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An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility
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Abstract:-This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional

FPGA Implementation of Low Power High Speed VLSI Architecture using Multirate Polyphase Filter
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RM Rewatkar, SL Badjate rspublication.com
Abstract: Paper Presents design and Implementation of Low Power high speed VLSI for Multirate Polyphase filter on FPGA platform. The proposed device is Polyphase decimator and interpolator, it design by direct and transpose form so that circuit complexity will be

A VLSI BASED LOW POWER APPROACH USING DYNAMIC VOLTAGE SCALING VOLTAGE ISLANDS FOR EMBEDDED PROCESSOR
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VLSI design efforts have mainly focused on optimizing speed to realize computationally on real time functions. Therefore, we maximize the run time and minimize the requirements to reduce the power consumption. Network On Chip is an IC approach to design the

Power Efficient Vlsi Architecture For High Throughput And Low Area Implementation Of Lifting 2-D Dwt
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JMD Babu, MB Sudha iosrjournals.org
Abstract: In this paper a new VLSI architecture was implemented for computation of lifting twodimensional (2-D) discrete wavelet transform (DWT). This structure was data transposition free and it was implemented by using linear systolic array which is derived

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vlsi using microwind



LFSR counter implementation in CMOS VLSI
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 Unlike most everyday devices whose inputs and operations are effectively predefined, VLSI chips must be able  and T3 are turned ON and new latched value passes to slave through the loop  the above designs of D Flip Flop with different components using Microwind 3.1 CMOS 

Design of low power phase locked loop (PLL) using 45nm VLSI Technology
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 current through P1 is mirrored by P2, P2, and P4.  in Digital Electronics from SGB Amravati University, Amravati in 2004pursuing Ph.D. Degree in Electronics Engineering with specialization in  Her interests are in Micro Electronic System Design using VLSI /CMOS 

4-Bit Fast Adder Design: Topology and Layout with Self-Resetting Logic for Low Power VLSICircuits
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 Addition is a fundamental arithmetic operation that is generally used in many VLSI systems, such  of primitive and adder circuits are elucidated and it is simulated using microwind and LT  Charge may be lost via charge sharing, noise injection due to capacitive coupling, charge 

Area, Delay and Power Comparison of Adder Topologies
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the incoming carry is forwarded immediately to the next block through the bypass and if it is not the case, the carry is obtained via the normal route.  Using this physical layout  International Journal of VLSI designCommunication Systems (VLSICS) Vol.3, No.1, February 2012 

Teaching CMOS Circuit Design in Nanoscale Technologies Using Microwind
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I am satisfied with the project-based learning approach used in the VLSI Design course  Using project-based learning methodologies suited to the teaching context, digital and analog IC  to the production of a range of learning resources to support students through project-based 

 Deep Submicron Technology
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S Govindarajulu, DTJ Prasad ,International Journal of Engineering , 2010  Dynamic domino logic circuits are widely used in modern digital VLSI circuits  and domino logic implementations are compared by simulation in deep submicron technology using MICROWIND3 CAD  is the power dissipation due to leakage currents which flow through a transistor 

Digital Nano-CMOS VLSI Design Courses in Electrical and Computer Engineering ThroughOpen-Source/Free Tools
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 The home directories of the students are also mounted, upon login, to the local workstation via NFS, or, if the workstation  AND EXTENSIONS We presented in this paper a conceptual organization of a digital, standard-cell based VLSI design flow using exclusively open 

DESIGN OF PULSE TRIGGERED FLIP FLOP USING PULSE ENHANCEMENT SCHEME
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A Selvakumar, T Prabakaran ,2012  as high as 20%-45% of the total system power[1]. In recent VLSI's, a clocking  3. SCCER: A refined low power P-FF design named SCCER using a conditional discharged technique  discharged through four transistors in series, ie, N1 through N4, while combating with the pull up 

Design performance of CMOS Circuits in Microwind
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NP Bobade, RH Umbarkar, UB Priyanka, SV Kohale ,2012 ,core.kmi.open.ac.uk  the experience in teaching integrated circuit design using an educational tool called Microwind through a Project  table 1 below shows the results of 8-bit ripple carry adder using CMOS circuits  The circuit and its VLSI technology is very useful in the applications related to rural 

Design performance of CMOS Circuits in Microwind
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NP Bobade, RH Umbarkar, UB Priyanka, SV Kohale ,2012 ,core.kmi.open.ac.uk ABSTRACT This paper describes the experience in teaching integrated circuit design using an educational tool called Microwind through a Project-Based Learning approach. The demand and popularity of portable electronics is driving designers to strive for small 

Teaching CMOS Circuit Design in Nanoscale Technologies Using Microwind
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ABSTRACT-This paper describes the experience in teaching integrated circuit design using an educational tool called Microwind through a Project-Based Learning approach. The evolution of the tool in the context of technology scale down is described, with focus on 



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