Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
Structured ASIC, which consists of a homogeneous array of tiles, suffers from large delay and area due to its inherent regularity. A new lithography method called selectively patterned masks (SPM) is proposed. It exploits special masks called masking masks and double exposure technique to allow more than one types of tiles to be patterned on […]
AN ASIC IMPLEMENTATION OF THE TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM
Image data compression has been an active research area for image processing over the last decade and has been used in a variety of applications. This thesis investigates the implementation of an image data compression method with VLSI hardware that could be used in practical coding systems to compress real-time video signals. In practical situations, […]
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE
Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. […]