Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
FREE-DOWNLOAD X Zhao, DL Lewis, HHS Lee… – … -AIDED DESIGN OF …, 2011 – 30, NO. 5, MAY 2011 Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs However, pre-bond testability presents unique challenges to 3-D clock tree design. First, each die needs a complete 2-D clock tree to enable pre-bond test THREE-DIMENSIONAL system integration […]
Single Chip Sensor Node Processor with Communication Centric Design
FREE-DOWNLOAD S Izumi, T Takeuchi, T Matsuda, H Lee… – IEICE Transactions …, 2010 – are the power reduction of RF circuit or processors. Thus, the communication centric design is strongly requested to reduce the power consumption of the RF circuits The architecture of proposal sensor node LSI is ad- dressed in Sect.3. Section 4 describes VLSI implementation
LARGE VLSI ARRAYS–POWER AND ARCHITECTURAL PERSPECTIVES
FREE-DOWNLOAD A Teman, O Yadid-Pecht… – INFORMATION TECHNOLOGIES & …, 2010 – These facts lead us to realization that low power solutions for embedded arrays are a necessity in modern VLSI design. Many techniques and solutions have been developed for power reduction in each type of array, but rarely has one technique been adapted to fit