Low power input output port design using clock gating technique
FREE-DOWNLOAD H Yang, CA Bulucea, N Kalamani… – … and Computers in …, 2010 – wseas.us is regarded as one of the effective logic in RTL and architectural power reduction [2]. Clock Roy, K. Vijaykumar, TN DCG: deterministic clock-gating for low-power microprocessor design; research Transactions on Very Large Scale Integration(VLSI) Systems
Tutorial on Battery Simulation-Matching Power Source to Electronic System
FREE-DOWNLOAD M Kulkarni… – Proc. 14th research VLSI Design and Test …, 2010 chips, the influence of power reduction on battery lifetime is important for portable devices. an electrical circuit model to simulate the performance of a battery as it powers the operation of a digital circuit. For a hypothetical electronic system containing 70 million gates implemented […]
Minimum energy cmos design with dual subthreshold supply and multiple logic-level gates
FREE-DOWNLOAD K Kim… – … Symposium on Quality Electronic Design, 2011 – eng.auburn.edu in MTCMOS Kim and VD Agrawal, “True Minimum Energy Design Using Dual Below-Threshold Supply Voltages,” in Proceedings of 24th International Conference on VLSI Design