An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
FREE-DOWNLOADJC Rau, CL Wu… – Tamkang Journal of Science and Engineering, 2011 – Full scan testing, one of the DFT (design-for-testability) technique, is a strategy based on full-scan design by changing all the storage elements into scan cells and stitch them together to form to single or multiple scan chains. In a full-scan design circuit, […]
Post Sign-off Leakage Power Optimization
FREE-DOWNLOAD H Abrishami, J Lou, J Qin, J Froessl… – 2011 These positive slacks can be traded for leakage power reduction. Although this paper is one of the few works that considers the post sign-off leakage power optimization, it still applies GBA It is used in the different stages of the VLSI design flow from synthesis to physical design
Robust design of power-efficient VLSI circuits
FREE-DOWNLOAD M Pedram – … the 2011 international symposium on Physical design, 2011 – Massoud Pedram University of Southern California Dept. of Electrical Engineering Presentation at ISPD March 28, 2011 Robust Design of Power-Efficient VLSI Circuits Page 2. M. Pedram Outline • Background and Motivation • Key Problem: Robust & Energy-Efficient Design