impact of layout on device
Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs FREE-DOWNLOAD [PDF] DV Kumar, K Narasimhulu, PS Reddy… – Electron Devices Abstract—Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel be- havior in the sub-100-nm regime. In this paper, we have quantified the performance […]
layout-educated analog design flow
FREE-DOWNLOAD [PDF] V Bourguet, L De Lamarre… – Circuits and Systems, … Abstruct- In this paper, we present a new flow for analog de- sign automation. It is an electrical and layout co-design flow which is based on the precise knowledge of the process electrical models and layout. This flow is as fast as a layout-aware flow since the layout
pre-layout extraction
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis FREE-DOWNLOAD [PDF] RF Badaoui, H Sampath, A Agarwal… – Proceedings of the 14th ABSTRACT This paper presents a high-level language MSL, for the specifica- tion of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing […]