Comparative analysis of two operational ampliﬁer topologies for ADC
This paper describes a comparative analysis between two topologies of operational ampliﬁers to design a 40 MS/s 12-Bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35µm AMS CMOS technology with 3.3V single power supply. The capacitors and selected operational ampliﬁers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational ampliﬁers with gain boosting.
Today, high performance analog to digital converters are a key element for the development of high performance mixed signal systems like image sensors. In the last years designers are developing analog to digital converters to achieve higher conversion speeds while reducing power consumption. This is special important for portable devices, a growing up sector in current user electronics. In fact the global performance of many integrated applications is limited by the performance of the ADC. Pipelined ADCs are a popular architecture for high-speed data conversion (10-100 MS/s) at medium to high resolution (8-14 bits). Within this architecture, residue ampliﬁers are known to dominate power dissipation due to the simultaneous demand for low noise, high speed, and precise linear ampliﬁcation. This is especially true for the ampliﬁers in the ﬁrst few-stages of the pipeline, which have the greatest impact on the ADCs overall performance. In this paper, we have compared two topologies of operational ampliﬁer (Opamp) using transient and AC simulations. The topology that reached the best performances was used to design a 40 MS/s 12-Bit Pipelined ADC whose measured results are shown in the last section. Besides of this comparison, several techniques have been developed to reduce the power dissipation. Basic low-power design approaches include stage scaling and optimization of the per-stage resolution and an optimal topology of the operational ampliﬁer. The rest of the paper is organised as follows. In section II we explain the ADC architecture. A comparison between the opamps is described in section III. In section IV measurement results of the implemented ADC are shown. Finally we conclude in section V.
The topology of this pipeline ADC is based on a conversion of 1.5 effective bit per stage, whose diagram is shown in Fig. 1. Process and circuit non idealities affect the transfer characteristic which result in a conversion factor different from two. These non-idealities include capacitor mismatches, offsets, etc. There are two possibilities to circumvent this. The ﬁrst is to set the factor AV to a nominal value smaller than 2, and the second is to increase redundancy by choosing 1.5 bit/stage . The pipeline consists of 11 stages. Each one of the ﬁrst ten stages performs a 2 bit quantization.
Comparative analysis of two operational ampliﬁer topologies for a 40MS/s 12-bit pipelined ADC in 0.35µm CMOS