Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology ijtsrd
In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average […]
Efficient Design of 2 1 MUX Multiplexer using Nanotechnology Based on QCA IJTSRD
Quantum Dot Cellular Automata is a new technology which overcomes of the of CMOS limitations. It is an novel advanced nano-technology that revolves around the single-electron position control. It is one of the most efficient and emerging nano-technology which mainly deals with the effect of electrons inside the quantum dots in QCA cell, and it […]