vlsi research papers 2012

vlsi research papers 2012




VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing
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ABSTRACT Sparse signal recovery finds use in a variety of practical applications, such as signal and image restoration and the recovery of signals acquired by compressive sensing. In this paper, we present two generic VLSI architectures that implement the approximate

VLSI Implementation of Hard-and Soft-Output Sphere Decoding for Wide-Band MIMO Systems
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Multiple-input multiple-output (MIMO) technology in combination with orthogonal frequency- division multiplexing (OFDM) is the key to meet the demands for data rate and link reliability of modern wide-band wireless communication systems, such as IEEE 802.11 n or 3GPP-

Genetic Algorithms based Partitioning of VLSI Circuit Systems
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ABSTRACT Circuit partitioning problem is a well known NP hard problem. The potential of Genetic Algorithm has been used to solve many computationally intensive problems (NP hard problems) because existing conventional methods are unable to perform the

Efficient VLSI Architecture for Low Complexity Parallel Reed Solomon Decoder
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ABSTRACT Reed Solomon code is one of the well-known Forward Error Correction (FEC) techniques. These codes are dealing with encoding and decoding of message sequence in terms of polynomials. This paper presents a parallel Reed Solomon decoder which

Power problems in VLSI circuit testing
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Controlling or reducing power consumption during test and reducing test time are conflicting goals. Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits.

VLSI Implementation of Scalable Encryption Algorithm for Different Text and Processor Size
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ABSTRACT The Efficiency of present symmetric encryption algorithms mainly depends on implementation cost and resulting performances. Present symmetric encryption, like the Advanced Encryption Standard (AES) rather focus on finding a good tradeoff between cost

Algorithm for Designing VLSI Floorplan using Planar Triangulated Graph
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ABSTRACT Floorplanning is a very crucial step in VLSI physical design. This paper presents a simple algorithm based on the concept of Planar Triangulated Graph (PTG) to place modules of a circuit dual graph on a floorplan. This algorithm places the modules on a

Global approaches for facility layout and VLSI floorplanning
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This chapter provides an overview of conic optimization models for facility layout and VLSI floorplanning problems. We focus on two classes of problems to which conic optimization approaches have been successfully applied, namely the single-row facility layout problem

An Efficient VLSI Design Approach to Reduce Static Power for Nano Scale CMOS VLSISystems using Variable Body Biasing
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ABSTRACT The development of digital integrated circuits is challenged by higher power consumption. In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to

Algorithm and VLSI Architecture for Real-Time 1080p60 Video Retargeting
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ABSTRACT Aspect ratio retargeting for streaming video has actively been researched in the past years. While the mobile market with its huge diversity of screen formats is one of the most promising application areas, no existing algorithm is efficient enough to be

Progress and Challenges in VLSI Placement Research
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Abstract Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been

A Novel Method for Analysis of Power Consumption in VLSI Global Interconnects
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ABSTRACT The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. We study the trends of

Using Electric VLSI Design system
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Layout technologies in Electric can be described by Xml technology files. These files are automatically generated by the technology editor and the technology- creation wizard, but some users may prefer to edit them by hand. For these users, the following is a description

An automated design approach of dependable VLSI using improved Canary FF
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ABSTRACT The demand of power saving and highly efficient LSI has increased by the miniaturization of semiconductor technology and the spread of portable device such as a mobile phone. We propose an automated design approach of dependable VLSI that

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design
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ABSTRACT In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold

Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style
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ABSTRACT Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs
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Abstract The design of Fast Fourier Transform (FFT) integrated architectures for System-on- Chip (SoC) telecom applications is addressed in this paper. After reviewing the FFT processing requirements of wireless and wired Orthogonal Frequency Division

The complexity of VLSI power-delay optimization by interconnect resizing
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ABSTRACT The lithography used for 32 nanometers and smaller VLSI process technologies restricts the interconnect widths and spaces to a very small set of admissible values. Until recently the sizes of interconnects were allowed to change continuously and the implied

Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
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Abstract Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In

Implementation of LFSR Counter Using CMOS VLSI Technology
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CMOS stands for Complementary Metal Oxide Semiconductor. It is basically a class of integrated circuits, and is used in a range of applications with digital logic circuits, such as microprocessors, microcontrollers, static RAM, etc. It is also used in applications with

Channel Height Estimation for VLSI Design
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Given an instance of channel routing problem (CRP) in VLSI design, the number of tracks used in a solution for the instance is called the channel height of the solution. The objective of CRP is to minimize the channel heights, that is, to find a solution with minimum channel

A simple VLSI architecture for computation of 2D DCT, quantisation and zig–zag ordering for JPEG
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In this paper, a comparative simulation study of Peak Signal to Noise Ratio (PSNR) in JPEG image compression is done using two quantisation tables, one recommended by JPEG committee and another suitable for hardware simplification. Simulation results confirm that

MATHEMATICAL MODELING OF BANDWIDTH AND POWER IN HIGH SPEED VLSI RLC INTERCONNECT WITH SKIN EFFECT
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Abstract As the interconnect technology is shrinking into nanometres regime the bandwidth of long interconnects reduces. Hence an accurate modelling of bandwidth is essential for the estimation of performance of VLSI interconnects. With the increase in

VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement Speech Enhancement
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ABSTRACT The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service,

Galeorstack-A Novel Leakage Reduction Technique for Low Power VLSI Design
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ABSTRACT Leakage power consumption plays a significant role in current CMOS technology. International Technology Roadmap for semiconductors reports that leakage power consumption dominates the total chip power consumption as technology advances

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