vlsi standard cell research papers
A procedure for placement of standard cell VLSI circuits
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ABSTRACT This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each
Place and route for secure standard cell design
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Side channel attacks can be effectively addressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced capacitive load at the differential outputs of the logic gates. The main contribution to this load is the capacitance
A performance-driven standard-cell placer based on a modified force-directed algorithm
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Abstract We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip
Area, delay, and power characteristics of standard-cell implementations of the AES S-box
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Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, whereby hardware designs for FPGAs
Development of a radiation tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments
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ABSTRACT A standard cell library was developed using a commercial 0.24 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on the layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library
Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology
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ABSTRACT This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and
Automatic layout of analog and digital mixed macro/standard cell integrated circuits
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Page 1. Automatic Layout of Analog and Digital Mixed Macro/Standard Cell Integrated Circuits William Swartz Yale University Page 2. Outline ? Introduction Core region I/O pad Page 11. Tour of Mixed Macro / Standard Cell Physical Design MSG Control Flow Cluster MC_route
Character-build standard-cell layout technique for high-throughput character-projection EB lithography
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ABSTRACT EB direct writing technology for small-volume fabrication LSIs is cost-effective compared to optical lithography. The new standard cell layout technique called Character- Build cell is developed in order to increase the utilization ratio of character projection (CP
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
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Abstract Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for
Detecting context sensitive hotspots in standard cell libraries
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ABSTRACT Advances in lithography patterning have been the primary driving force in microelectronics manufacturing processes. With the increasing gap between the wavelength of the optical source and feature sizes, the accompanying strong diffraction effects have a
Low power design of standard cell digital VLSI circuits
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Recent work by Raja, et al., shows that a totally glitch-free design of the benchmark circuit c7552 consumes 62% less power than a nominal design. Their method incurs no increase in the overall delay of the circuit and requires setting of delays for all gates as specified by
Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology
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ABSTRACT In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable
Standard cell design with regularly placed contacts and gates
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Abstract The layout strategies of standard cells with regularly-placed contacts and gates are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows a reduction of critical dimensions. Although regular
On the Variation of the Electromotive Force of Different Forms of the Clark Standard Cell with Temperature and with Strength of Solution
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HL Callendar, HT Barnes , of the Royal , 1897 ,rspl.royalsocietypublishing.org Several comparisons of these portable cells were made early in 1894 at different dates and under ordinary laboratory conditions.. The results, when corrected for temperature by means of the enclosed thermometers, showed irregular differences, often amounting to nearly 3
The economics of structured-and standard-cell-ASIC designs
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RTL or netlist to tape-out constitutes the physical-design process. This process comprises synthesis, DFT (design for test), floorplanning, timing analysis, clock insertion, place and route, timing closure, reliability analysis, and physical-design verification. For FPGAs and
Studies of Clustering Objectives and Heuristics for Improved Standard-Cell Placement
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ABSTRACT This paper describes ongoing studies of clustering objectives and heuristics, along with their effect on top-down partitioning based standard-cell placement. Clustering for placement has three main facets the objective, the heuristic, and the benefits but the
Semi-Automated Design of a MOS Current-Mode Logic Standard Cell Library from Generic Components
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Abstract This paper describes the design and semi-automated generation of a MOS current-mode logic standard cell library. A set of generic components implementing a wide range of combinational and sequential functions is proposed. The layout of the generic
Shot number estimation for EB direct writing for logic LSI utilizing character-build standard-celllayout technique
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ABSTRACT Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool for small-volume logic-LSI fabrication. The EB exposure time will be greatly reduced by applying character-projection (CP) aperture. But the applicable number of CP
Digital standard cell library migration using a genetic approach
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ABSTRACT Digital standard cell libraries are a key element in every modern VLSI design flow. The most important issues are compactness and speed of the cells. Therefore, the performance of these cells and their layout are individually tuned. This job is not only
A genetic approach to standard cell placement using various genetic operators
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ABSTRACT Genetic algorithm (GA) is a powerful optimization algorithm, which starts with an initial set of random configurations and uses a process similar to biological evolution to improve upon them . As we know that there is a progression towards miniaturization.
An Island-Based GA Implementation for VLSI Standard-Cell Placement
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Genetic algorithms require relatively large computation time to solve optimization problems, especially in VLSI CAD such as module placement. Therefore, island-based parallel GAs are used to speed up this procedure. The migration schemes that most researchers
Implementation of silicon-validated variability analysis and optimization for standard celllibraries
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ABSTRACT Leveraging silicon validation, a model-based variability analysis has been implemented to detect sensitivity to systematic variations in standard cell libraries using a model-based solution, to reduce performance spread at the cell level and chip level. First,
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