Analysis of Crosstalk-Affected Propagation Delay of VLSI Interconnect in Nanometer Technologies
FREE-DOWNLOADS Nazarian… – Int’l Journal of Electronics, 2010 . Therefore as the VLSI technology scales down the role of interconnect parasitic effects in the signal integrity becomes increasingly more pronounced. Another unwanted side effect of CMOS process technology scaling is the increase in process variations
Reconfigurable Computing in the New Age of Parallelism
FREE-DOWNLOAD W Najjar… – Embedded Computer Systems: Architectures, . Today, VLSI technology has reached a point where the shrinking of the feature size of transistors faces major technological barriers. The number of dopant ions in a single device has become so small that it poses a risk to the stability of the device over time.
65 nm CMOS devices for Low Power Applications
FREE-DOWNLOADK Bailey, KS Gurumurthy, CA Bulucea… – … and Computers in …, 2010 This paper attempts to analyze the performance of 65 nm CMOS device structures for low power applications. It indicates that the historical trend of scaling of MOS devices can be sustained by innovative CMOS Structures such as Ultra-thin body SOI devices and […]